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Searched refs:REG_SC_BK01_24_L (Results 1 – 25 of 67) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_ip.c663 SC_W2BYTEMSK(0, REG_SC_BK01_24_L, u8Start<<8, 0xFF00 ); in Hal_SC_ip_set_coast_window()
969 SC_W2BYTEMSK(0, REG_SC_BK01_24_L, ((bInputSel<<5)|BIT(0)), 0xFF ); in Hal_SC_ip_set_coast_input()
1786 value = SC_R2BYTE(0,REG_SC_BK01_24_L); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_ip.c663 SC_W2BYTEMSK(0, REG_SC_BK01_24_L, u8Start<<8, 0xFF00 ); in Hal_SC_ip_set_coast_window()
969 SC_W2BYTEMSK(0, REG_SC_BK01_24_L, ((bInputSel<<5)|BIT(0)), 0xFF ); in Hal_SC_ip_set_coast_input()
1786 value = SC_R2BYTE(0,REG_SC_BK01_24_L); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_ip.c654 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, u8Start<<8, 0xFF00 ); in Hal_SC_ip_set_coast_window()
941 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, ((bInputSel<<1)|BIT(0)), 0xFF ); in Hal_SC_ip_set_coast_input()
2086 value = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_24_L); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_ip.c740 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, u8Start<<8, 0xFF00 ); in Hal_SC_ip_set_coast_window()
1074 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, ((bInputSel<<5)|BIT(0)), 0xFF ); in Hal_SC_ip_set_coast_input()
2217 value = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_24_L); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_ip.c787 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, u8Start<<8, 0xFF00 ); in Hal_SC_ip_set_coast_window()
1121 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, ((bInputSel<<5)|BIT(0)), 0xFF ); in Hal_SC_ip_set_coast_input()
2211 value = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_24_L); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_ip.c740 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, u8Start<<8, 0xFF00 ); in Hal_SC_ip_set_coast_window()
1074 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, ((bInputSel<<5)|BIT(0)), 0xFF ); in Hal_SC_ip_set_coast_input()
2204 value = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_24_L); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_ip.c740 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, u8Start<<8, 0xFF00 ); in Hal_SC_ip_set_coast_window()
1074 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, ((bInputSel<<5)|BIT(0)), 0xFF ); in Hal_SC_ip_set_coast_input()
2204 value = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_24_L); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_ip.c744 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, u8Start<<8, 0xFF00 ); in Hal_SC_ip_set_coast_window()
1078 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, ((bInputSel<<5)|BIT(0)), 0xFF ); in Hal_SC_ip_set_coast_input()
2206 value = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_24_L); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_ip.c654 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, u8Start<<8, 0xFF00 ); in Hal_SC_ip_set_coast_window()
941 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, ((bInputSel<<1)|BIT(0)), 0xFF ); in Hal_SC_ip_set_coast_input()
2085 value = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_24_L); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_ip.c654 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, u8Start<<8, 0xFF00 ); in Hal_SC_ip_set_coast_window()
941 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, ((bInputSel<<1)|BIT(0)), 0xFF ); in Hal_SC_ip_set_coast_input()
2085 value = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_24_L); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_ip.c743 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, u8Start<<8, 0xFF00 ); in Hal_SC_ip_set_coast_window()
1077 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, ((bInputSel<<5)|BIT(0)), 0xFF ); in Hal_SC_ip_set_coast_input()
2177 value = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_24_L); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_ip.c654 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, u8Start<<8, 0xFF00 ); in Hal_SC_ip_set_coast_window()
941 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, ((bInputSel<<1)|BIT(0)), 0xFF ); in Hal_SC_ip_set_coast_input()
2085 value = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_24_L); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_ip.c744 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, u8Start<<8, 0xFF00 ); in Hal_SC_ip_set_coast_window()
1078 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, ((bInputSel<<5)|BIT(0)), 0xFF ); in Hal_SC_ip_set_coast_input()
2206 value = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_24_L); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_ip.c743 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, u8Start<<8, 0xFF00 ); in Hal_SC_ip_set_coast_window()
1077 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, ((bInputSel<<5)|BIT(0)), 0xFF ); in Hal_SC_ip_set_coast_input()
2177 value = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_24_L); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_ip.c740 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, u8Start<<8, 0xFF00 ); in Hal_SC_ip_set_coast_window()
1074 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK01_24_L, ((bInputSel<<5)|BIT(0)), 0xFF ); in Hal_SC_ip_set_coast_input()
2217 value = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_24_L); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/wble/hal/manhattan/wble/include/
H A Dhwreg_wble.h442 #define REG_SC_BK01_24_L _PK_L_(0x01, 0x24) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/include/
H A Dhwreg_ace.h442 #define REG_SC_BK01_24_L _PK_L_(0x01, 0x24) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A Dhwreg_dlc.h444 #define REG_SC_BK01_24_L _PK_L_(0x01, 0x24) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/include/
H A Dhwreg_ace.h442 #define REG_SC_BK01_24_L _PK_L_(0x01, 0x24) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A Dhwreg_dlc.h444 #define REG_SC_BK01_24_L _PK_L_(0x01, 0x24) macro
/utopia/UTPA2-700.0.x/modules/wble/hal/macan/wble/include/
H A Dhwreg_wble.h442 #define REG_SC_BK01_24_L _PK_L_(0x01, 0x24) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A Dhwreg_dlc.h444 #define REG_SC_BK01_24_L _PK_L_(0x01, 0x24) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/ace/include/
H A Dhwreg_ace.h442 #define REG_SC_BK01_24_L _PK_L_(0x01, 0x24) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7821/dlc/include/
H A Dhwreg_dlc.h444 #define REG_SC_BK01_24_L _PK_L_(0x01, 0x24) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/ace/include/
H A Dhwreg_ace.h442 #define REG_SC_BK01_24_L _PK_L_(0x01, 0x24) macro

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