| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/ |
| H A D | halMHL.c | 691 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
692 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
696 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
697 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
701 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(3:1), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
702 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(0), BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
715 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
716 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
720 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
721 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
[all …]
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/ |
| H A D | halMHL.c | 707 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
708 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
712 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
713 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
717 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(3:1), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
718 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(0), BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
731 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
732 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
736 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
737 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
[all …]
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/ |
| H A D | halMHL.c | 754 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
755 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
759 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
760 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
764 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(3:1), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
765 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(0), BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
775 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
776 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
780 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
781 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
[all …]
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/ |
| H A D | halMHL.c | 754 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
755 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
759 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
760 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
764 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(3:1), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
765 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(0), BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
775 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
776 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
780 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
781 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
[all …]
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/ |
| H A D | halMHL.c | 754 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
755 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
759 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
760 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
764 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(3:1), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
765 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(0), BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
775 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
776 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
780 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
781 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
[all …]
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/ |
| H A D | halMHL.c | 754 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
755 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
759 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
760 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
764 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(3:1), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
765 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(0), BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
775 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
776 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
780 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
781 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
[all …]
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/ |
| H A D | halMHL.c | 754 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
755 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
759 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
760 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
764 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(3:1), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
765 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(0), BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
775 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
776 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
780 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
781 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 1897 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xFFFF); // [3:0]: port reg_pd_rt in Hal_HDMI_init()
3004 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(0) : 0, BIT(0)); in Hal_DVI_ClkPullLow()
3007 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(4) : 0, BIT(4)); in Hal_DVI_ClkPullLow()
3010 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(8) : 0, BIT(8)); in Hal_DVI_ClkPullLow()
3013 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12) : 0, BIT(12)); in Hal_DVI_ClkPullLow()
3016 …PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12)|BIT(8)|BIT(4)|BIT(0) : 0, BIT(12)|BIT(8)|BIT(4)|BI… in Hal_DVI_ClkPullLow()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 4019 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x000F); // [3:0]: port0 reg_pd_rt in Hal_HDMI_init()
4024 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x00F0); // [7:4]: port1 reg_pd_rt in Hal_HDMI_init()
4029 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x0F00); // [11:8]: port2 reg_pd_rt in Hal_HDMI_init()
4034 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xF000); // [15:12]: port3 reg_pd_rt in Hal_HDMI_init()
4059 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xFFFF); // DVI clock power on in Hal_HDMI_init()
5351 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(0) : 0, BIT(0)); in Hal_DVI_ClkPullLow()
5354 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(4) : 0, BIT(4)); in Hal_DVI_ClkPullLow()
5357 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(8) : 0, BIT(8)); in Hal_DVI_ClkPullLow()
5360 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12) : 0, BIT(12)); in Hal_DVI_ClkPullLow()
5363 …PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12)|BIT(8)|BIT(4)|BIT(0) : 0, BIT(12)|BIT(8)|BIT(4)|BI… in Hal_DVI_ClkPullLow()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 4124 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x000F); // [3:0]: port0 reg_pd_rt in Hal_HDMI_init()
4129 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x00F0); // [7:4]: port1 reg_pd_rt in Hal_HDMI_init()
4134 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x0F00); // [11:8]: port2 reg_pd_rt in Hal_HDMI_init()
4139 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xF000); // [15:12]: port3 reg_pd_rt in Hal_HDMI_init()
4166 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xFFFF); // DVI clock power on in Hal_HDMI_init()
5451 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(0) : 0, BIT(0)); in Hal_DVI_ClkPullLow()
5454 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(4) : 0, BIT(4)); in Hal_DVI_ClkPullLow()
5457 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(8) : 0, BIT(8)); in Hal_DVI_ClkPullLow()
5460 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12) : 0, BIT(12)); in Hal_DVI_ClkPullLow()
5463 …PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12)|BIT(8)|BIT(4)|BIT(0) : 0, BIT(12)|BIT(8)|BIT(4)|BI… in Hal_DVI_ClkPullLow()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 4133 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x000F); // [3:0]: port0 reg_pd_rt in Hal_HDMI_init()
4138 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x00F0); // [7:4]: port1 reg_pd_rt in Hal_HDMI_init()
4143 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x0F00); // [11:8]: port2 reg_pd_rt in Hal_HDMI_init()
4148 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xF000); // [15:12]: port3 reg_pd_rt in Hal_HDMI_init()
4173 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xFFFF); // DVI clock power on in Hal_HDMI_init()
5493 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(0) : 0, BIT(0)); in Hal_DVI_ClkPullLow()
5496 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(4) : 0, BIT(4)); in Hal_DVI_ClkPullLow()
5499 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(8) : 0, BIT(8)); in Hal_DVI_ClkPullLow()
5502 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12) : 0, BIT(12)); in Hal_DVI_ClkPullLow()
5505 …PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12)|BIT(8)|BIT(4)|BIT(0) : 0, BIT(12)|BIT(8)|BIT(4)|BI… in Hal_DVI_ClkPullLow()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 4124 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x000F); // [3:0]: port0 reg_pd_rt in Hal_HDMI_init()
4129 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x00F0); // [7:4]: port1 reg_pd_rt in Hal_HDMI_init()
4134 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x0F00); // [11:8]: port2 reg_pd_rt in Hal_HDMI_init()
4139 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xF000); // [15:12]: port3 reg_pd_rt in Hal_HDMI_init()
4166 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xFFFF); // DVI clock power on in Hal_HDMI_init()
5451 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(0) : 0, BIT(0)); in Hal_DVI_ClkPullLow()
5454 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(4) : 0, BIT(4)); in Hal_DVI_ClkPullLow()
5457 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(8) : 0, BIT(8)); in Hal_DVI_ClkPullLow()
5460 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12) : 0, BIT(12)); in Hal_DVI_ClkPullLow()
5463 …PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12)|BIT(8)|BIT(4)|BIT(0) : 0, BIT(12)|BIT(8)|BIT(4)|BI… in Hal_DVI_ClkPullLow()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 4064 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x000F); // [3:0]: port0 reg_pd_rt in Hal_HDMI_init()
4069 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x00F0); // [7:4]: port1 reg_pd_rt in Hal_HDMI_init()
4074 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x0F00); // [11:8]: port2 reg_pd_rt in Hal_HDMI_init()
4079 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xF000); // [15:12]: port3 reg_pd_rt in Hal_HDMI_init()
4104 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xFFFF); // DVI clock power on in Hal_HDMI_init()
5466 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(0) : 0, BIT(0)); in Hal_DVI_ClkPullLow()
5469 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(4) : 0, BIT(4)); in Hal_DVI_ClkPullLow()
5472 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(8) : 0, BIT(8)); in Hal_DVI_ClkPullLow()
5475 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12) : 0, BIT(12)); in Hal_DVI_ClkPullLow()
5478 …PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12)|BIT(8)|BIT(4)|BIT(0) : 0, BIT(12)|BIT(8)|BIT(4)|BI… in Hal_DVI_ClkPullLow()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 4133 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x000F); // [3:0]: port0 reg_pd_rt in Hal_HDMI_init()
4138 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x00F0); // [7:4]: port1 reg_pd_rt in Hal_HDMI_init()
4143 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x0F00); // [11:8]: port2 reg_pd_rt in Hal_HDMI_init()
4148 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xF000); // [15:12]: port3 reg_pd_rt in Hal_HDMI_init()
4173 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xFFFF); // DVI clock power on in Hal_HDMI_init()
5493 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(0) : 0, BIT(0)); in Hal_DVI_ClkPullLow()
5496 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(4) : 0, BIT(4)); in Hal_DVI_ClkPullLow()
5499 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(8) : 0, BIT(8)); in Hal_DVI_ClkPullLow()
5502 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12) : 0, BIT(12)); in Hal_DVI_ClkPullLow()
5505 …PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12)|BIT(8)|BIT(4)|BIT(0) : 0, BIT(12)|BIT(8)|BIT(4)|BI… in Hal_DVI_ClkPullLow()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 4695 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x000F); // [3:0]: port0 reg_pd_rt in Hal_HDMI_init()
4700 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x00F0); // [7:4]: port1 reg_pd_rt in Hal_HDMI_init()
4705 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x0F00); // [11:8]: port2 reg_pd_rt in Hal_HDMI_init()
4710 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xF000); // [15:12]: port3 reg_pd_rt in Hal_HDMI_init()
4735 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xFFFF); // DVI clock power on in Hal_HDMI_init()
6054 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(0) : 0, BIT(0)); in Hal_DVI_ClkPullLow()
6057 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(4) : 0, BIT(4)); in Hal_DVI_ClkPullLow()
6060 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(8) : 0, BIT(8)); in Hal_DVI_ClkPullLow()
6063 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12) : 0, BIT(12)); in Hal_DVI_ClkPullLow()
6066 …PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12)|BIT(8)|BIT(4)|BIT(0) : 0, BIT(12)|BIT(8)|BIT(4)|BI… in Hal_DVI_ClkPullLow()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 4698 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x000F); // [3:0]: port0 reg_pd_rt in Hal_HDMI_init()
4703 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x00F0); // [7:4]: port1 reg_pd_rt in Hal_HDMI_init()
4708 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x0F00); // [11:8]: port2 reg_pd_rt in Hal_HDMI_init()
4713 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xF000); // [15:12]: port3 reg_pd_rt in Hal_HDMI_init()
4738 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xFFFF); // DVI clock power on in Hal_HDMI_init()
6057 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(0) : 0, BIT(0)); in Hal_DVI_ClkPullLow()
6060 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(4) : 0, BIT(4)); in Hal_DVI_ClkPullLow()
6063 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(8) : 0, BIT(8)); in Hal_DVI_ClkPullLow()
6066 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12) : 0, BIT(12)); in Hal_DVI_ClkPullLow()
6069 …PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12)|BIT(8)|BIT(4)|BIT(0) : 0, BIT(12)|BIT(8)|BIT(4)|BI… in Hal_DVI_ClkPullLow()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 4255 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x000F); // [3:0]: port0 reg_pd_rt in Hal_HDMI_init()
4260 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x00F0); // [7:4]: port1 reg_pd_rt in Hal_HDMI_init()
4265 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x0F00); // [11:8]: port2 reg_pd_rt in Hal_HDMI_init()
4270 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xF000); // [15:12]: port3 reg_pd_rt in Hal_HDMI_init()
4295 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xFFFF); // DVI clock power on in Hal_HDMI_init()
5764 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(0) : 0, BIT(0)); in Hal_DVI_ClkPullLow()
5767 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(4) : 0, BIT(4)); in Hal_DVI_ClkPullLow()
5770 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(8) : 0, BIT(8)); in Hal_DVI_ClkPullLow()
5773 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12) : 0, BIT(12)); in Hal_DVI_ClkPullLow()
5776 …PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12)|BIT(8)|BIT(4)|BIT(0) : 0, BIT(12)|BIT(8)|BIT(4)|BI… in Hal_DVI_ClkPullLow()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 4701 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x000F); // [3:0]: port0 reg_pd_rt in Hal_HDMI_init()
4706 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x00F0); // [7:4]: port1 reg_pd_rt in Hal_HDMI_init()
4711 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x0F00); // [11:8]: port2 reg_pd_rt in Hal_HDMI_init()
4716 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xF000); // [15:12]: port3 reg_pd_rt in Hal_HDMI_init()
4741 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xFFFF); // DVI clock power on in Hal_HDMI_init()
6060 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(0) : 0, BIT(0)); in Hal_DVI_ClkPullLow()
6063 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(4) : 0, BIT(4)); in Hal_DVI_ClkPullLow()
6066 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(8) : 0, BIT(8)); in Hal_DVI_ClkPullLow()
6069 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12) : 0, BIT(12)); in Hal_DVI_ClkPullLow()
6072 …PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12)|BIT(8)|BIT(4)|BIT(0) : 0, BIT(12)|BIT(8)|BIT(4)|BI… in Hal_DVI_ClkPullLow()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 4255 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x000F); // [3:0]: port0 reg_pd_rt in Hal_HDMI_init()
4260 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x00F0); // [7:4]: port1 reg_pd_rt in Hal_HDMI_init()
4265 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0x0F00); // [11:8]: port2 reg_pd_rt in Hal_HDMI_init()
4270 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xF000); // [15:12]: port3 reg_pd_rt in Hal_HDMI_init()
4295 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xFFFF); // DVI clock power on in Hal_HDMI_init()
5764 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(0) : 0, BIT(0)); in Hal_DVI_ClkPullLow()
5767 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(4) : 0, BIT(4)); in Hal_DVI_ClkPullLow()
5770 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(8) : 0, BIT(8)); in Hal_DVI_ClkPullLow()
5773 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12) : 0, BIT(12)); in Hal_DVI_ClkPullLow()
5776 …PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12)|BIT(8)|BIT(4)|BIT(0) : 0, BIT(12)|BIT(8)|BIT(4)|BI… in Hal_DVI_ClkPullLow()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 2632 PM_W2BYTE(REG_PM_SLEEP_4C_L, 0x0000, 0xFFFF); // [3:0]: port reg_pd_rt in Hal_HDMI_init()
3741 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(0) : 0, BIT(0)); in Hal_DVI_ClkPullLow()
3744 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(4) : 0, BIT(4)); in Hal_DVI_ClkPullLow()
3747 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(8) : 0, BIT(8)); in Hal_DVI_ClkPullLow()
3750 PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12) : 0, BIT(12)); in Hal_DVI_ClkPullLow()
3753 …PM_W2BYTE(REG_PM_SLEEP_4C_L, bPullLow ? BIT(12)|BIT(8)|BIT(4)|BIT(0) : 0, BIT(12)|BIT(8)|BIT(4)|BI… in Hal_DVI_ClkPullLow()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_pm_sleep.h | 253 #define REG_PM_SLEEP_4C_L (REG_PM_SLEEP_BASE + 0x98) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | hwreg_pm_sleep.h | 254 #define REG_PM_SLEEP_4C_L (REG_PM_SLEEP_BASE + 0x98) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | hwreg_pm_sleep.h | 254 #define REG_PM_SLEEP_4C_L (REG_PM_SLEEP_BASE + 0x98) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_pm_sleep.h | 253 #define REG_PM_SLEEP_4C_L (REG_PM_SLEEP_BASE + 0x98) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_pm_sleep.h | 253 #define REG_PM_SLEEP_4C_L (REG_PM_SLEEP_BASE + 0x98) macro
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