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Searched refs:REG_PM_SLEEP_4A_L (Results 1 – 25 of 39) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_mux.c384 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0xE000, 0xF000); // power on Port A DVI clockin in Hal_SC_mux_set_dvi_mux()
417 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0xD000, 0xF000); // power on Port B DVI clockin in Hal_SC_mux_set_dvi_mux()
450 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0xB000, 0xF000); // power on Port D DVI clockin in Hal_SC_mux_set_dvi_mux()
483 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x7000, 0xF000); // power on Port C DVI clockin in Hal_SC_mux_set_dvi_mux()
516 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0xF000, 0xF000); // power off DVI clockin in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c1083 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0xF000, 0xF000); // power off DVI off-line detection clock in Hal_HDMI_init()
1093 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0xFFFF); // DM and DVI clock power on in Hal_HDMI_init()
1143 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0xF000); // power on DVI off-line detection clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_mux.c384 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0xE000, 0xF000); // power on Port A DVI clockin in Hal_SC_mux_set_dvi_mux()
417 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0xD000, 0xF000); // power on Port B DVI clockin in Hal_SC_mux_set_dvi_mux()
450 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0xB000, 0xF000); // power on Port D DVI clockin in Hal_SC_mux_set_dvi_mux()
483 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x7000, 0xF000); // power on Port C DVI clockin in Hal_SC_mux_set_dvi_mux()
516 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0xF000, 0xF000); // power off DVI clockin in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c1083 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0xF000, 0xF000); // power off DVI off-line detection clock in Hal_HDMI_init()
1093 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0xFFFF); // DM and DVI clock power on in Hal_HDMI_init()
1143 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0xF000); // power on DVI off-line detection clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhalMHL.c1092 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(8): 0, BIT(8)); in _mhal_mhl_RtermHWControl()
1102 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(9): 0, BIT(9)); in _mhal_mhl_RtermHWControl()
1112 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(10): 0, BIT(10)); in _mhal_mhl_RtermHWControl()
1122 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(11): 0, BIT(11)); in _mhal_mhl_RtermHWControl()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhalMHL.c1108 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(8): 0, BIT(8)); in _mhal_mhl_RtermHWControl()
1118 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(9): 0, BIT(9)); in _mhal_mhl_RtermHWControl()
1128 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(10): 0, BIT(10)); in _mhal_mhl_RtermHWControl()
1138 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(11): 0, BIT(11)); in _mhal_mhl_RtermHWControl()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhalMHL.c1027 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(8): 0, BIT(8)); in _mhal_mhl_RtermHWControl()
1033 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(9): 0, BIT(9)); in _mhal_mhl_RtermHWControl()
1039 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(10): 0, BIT(10)); in _mhal_mhl_RtermHWControl()
1045 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(11): 0, BIT(11)); in _mhal_mhl_RtermHWControl()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhalMHL.c1027 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(8): 0, BIT(8)); in _mhal_mhl_RtermHWControl()
1033 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(9): 0, BIT(9)); in _mhal_mhl_RtermHWControl()
1039 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(10): 0, BIT(10)); in _mhal_mhl_RtermHWControl()
1045 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(11): 0, BIT(11)); in _mhal_mhl_RtermHWControl()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhalMHL.c1027 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(8): 0, BIT(8)); in _mhal_mhl_RtermHWControl()
1033 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(9): 0, BIT(9)); in _mhal_mhl_RtermHWControl()
1039 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(10): 0, BIT(10)); in _mhal_mhl_RtermHWControl()
1045 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(11): 0, BIT(11)); in _mhal_mhl_RtermHWControl()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhalMHL.c1027 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(8): 0, BIT(8)); in _mhal_mhl_RtermHWControl()
1033 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(9): 0, BIT(9)); in _mhal_mhl_RtermHWControl()
1039 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(10): 0, BIT(10)); in _mhal_mhl_RtermHWControl()
1045 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(11): 0, BIT(11)); in _mhal_mhl_RtermHWControl()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhalMHL.c1027 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(8): 0, BIT(8)); in _mhal_mhl_RtermHWControl()
1033 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(9): 0, BIT(9)); in _mhal_mhl_RtermHWControl()
1039 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(10): 0, BIT(10)); in _mhal_mhl_RtermHWControl()
1045 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(11): 0, BIT(11)); in _mhal_mhl_RtermHWControl()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c4018 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0001); // [0]: port0 reg_pd_clkin in Hal_HDMI_init()
4023 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0002); // [1]: port1 reg_pd_clkin in Hal_HDMI_init()
4028 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0004); // [2]: port2 reg_pd_clkin in Hal_HDMI_init()
4033 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0008); // [3]: port3 reg_pd_clkin in Hal_HDMI_init()
4058 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x000F); // power on DVI off-line detection clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c4123 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0001); // [0]: port0 reg_pd_clkin in Hal_HDMI_init()
4128 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0002); // [1]: port1 reg_pd_clkin in Hal_HDMI_init()
4133 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0004); // [2]: port2 reg_pd_clkin in Hal_HDMI_init()
4138 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0008); // [3]: port3 reg_pd_clkin in Hal_HDMI_init()
4165 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x000F); // power on DVI off-line detection clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c4132 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0001); // [0]: port0 reg_pd_clkin in Hal_HDMI_init()
4137 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0002); // [1]: port1 reg_pd_clkin in Hal_HDMI_init()
4142 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0004); // [2]: port2 reg_pd_clkin in Hal_HDMI_init()
4147 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0008); // [3]: port3 reg_pd_clkin in Hal_HDMI_init()
4172 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x000F); // power on DVI off-line detection clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c4123 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0001); // [0]: port0 reg_pd_clkin in Hal_HDMI_init()
4128 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0002); // [1]: port1 reg_pd_clkin in Hal_HDMI_init()
4133 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0004); // [2]: port2 reg_pd_clkin in Hal_HDMI_init()
4138 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0008); // [3]: port3 reg_pd_clkin in Hal_HDMI_init()
4165 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x000F); // power on DVI off-line detection clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c4063 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0001); // [0]: port0 reg_pd_clkin in Hal_HDMI_init()
4068 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0002); // [1]: port1 reg_pd_clkin in Hal_HDMI_init()
4073 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0004); // [2]: port2 reg_pd_clkin in Hal_HDMI_init()
4078 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0008); // [3]: port3 reg_pd_clkin in Hal_HDMI_init()
4103 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x000F); // power on DVI off-line detection clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c4132 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0001); // [0]: port0 reg_pd_clkin in Hal_HDMI_init()
4137 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0002); // [1]: port1 reg_pd_clkin in Hal_HDMI_init()
4142 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0004); // [2]: port2 reg_pd_clkin in Hal_HDMI_init()
4147 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0008); // [3]: port3 reg_pd_clkin in Hal_HDMI_init()
4172 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x000F); // power on DVI off-line detection clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c4694 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0001); // [0]: port0 reg_pd_clkin in Hal_HDMI_init()
4699 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0002); // [1]: port1 reg_pd_clkin in Hal_HDMI_init()
4704 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0004); // [2]: port2 reg_pd_clkin in Hal_HDMI_init()
4709 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0008); // [3]: port3 reg_pd_clkin in Hal_HDMI_init()
4734 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x000F); // power on DVI off-line detection clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c4697 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0001); // [0]: port0 reg_pd_clkin in Hal_HDMI_init()
4702 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0002); // [1]: port1 reg_pd_clkin in Hal_HDMI_init()
4707 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0004); // [2]: port2 reg_pd_clkin in Hal_HDMI_init()
4712 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0008); // [3]: port3 reg_pd_clkin in Hal_HDMI_init()
4737 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x000F); // power on DVI off-line detection clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c4254 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0001); // [0]: port0 reg_pd_clkin in Hal_HDMI_init()
4259 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0002); // [1]: port1 reg_pd_clkin in Hal_HDMI_init()
4264 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0004); // [2]: port2 reg_pd_clkin in Hal_HDMI_init()
4269 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0008); // [3]: port3 reg_pd_clkin in Hal_HDMI_init()
4294 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x000F); // power on DVI off-line detection clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c4700 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0001); // [0]: port0 reg_pd_clkin in Hal_HDMI_init()
4705 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0002); // [1]: port1 reg_pd_clkin in Hal_HDMI_init()
4710 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0004); // [2]: port2 reg_pd_clkin in Hal_HDMI_init()
4715 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0008); // [3]: port3 reg_pd_clkin in Hal_HDMI_init()
4740 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x000F); // power on DVI off-line detection clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c4254 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0001); // [0]: port0 reg_pd_clkin in Hal_HDMI_init()
4259 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0002); // [1]: port1 reg_pd_clkin in Hal_HDMI_init()
4264 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0004); // [2]: port2 reg_pd_clkin in Hal_HDMI_init()
4269 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x0008); // [3]: port3 reg_pd_clkin in Hal_HDMI_init()
4294 PM_W2BYTE(REG_PM_SLEEP_4A_L, 0x0000, 0x000F); // power on DVI off-line detection clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_pm_sleep.h249 #define REG_PM_SLEEP_4A_L (REG_PM_SLEEP_BASE + 0x94) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_pm_sleep.h250 #define REG_PM_SLEEP_4A_L (REG_PM_SLEEP_BASE + 0x94) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_pm_sleep.h250 #define REG_PM_SLEEP_4A_L (REG_PM_SLEEP_BASE + 0x94) macro

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