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Searched refs:REG_MOD_BASE (Results 1 – 25 of 69) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Dxc_hwreg_utility2.h560 ( { RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFFFF)) << 1 , u16Val ) ; } )
563 ( { RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFFFF)) <<1 ) ; } )
566 ( { RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFFFF)) << 1) & (u16mask) ; } )
569 …( { RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFFFF)) << 1, (RIU_READ_2BYTE( (REG_MOD_BASE + (…
576 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
577 RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1, u16Val ); } )
580 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
581 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) ; } )
584 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
585 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask); })
[all …]
/utopia/UTPA2-700.0.x/modules/dlc/drv/dlc/include/
H A Ddlc_hwreg_utility2.h224 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
225 RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1, u16Val ); } )
228 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
229 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) ; } )
232 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
233 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask); })
236 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
237 …RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) )<<1 , (RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Re…
/utopia/UTPA2-700.0.x/modules/wble/drv/wble/include/
H A Dwble_hwreg_utility2.h224 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
225 RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1, u16Val ); } )
228 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
229 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) ; } )
232 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
233 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask); })
236 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
237 …RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) )<<1 , (RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Re…
/utopia/UTPA2-700.0.x/modules/ddc2bi/drv/ddc2bi/include/
H A Dddc2bi_hwreg_utility2.h224 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
225 RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1, u16Val ); } )
228 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
229 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) ; } )
232 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
233 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask); })
236 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
237 …RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) )<<1 , (RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Re…
/utopia/UTPA2-700.0.x/modules/ve/drv/ve/include/
H A Dve_hwreg_utility2.h267 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
268 RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1, u16Val ); } )
271 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
272 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) ; } )
275 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
276 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask); })
279 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
280 …RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) )<<1 , (RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Re…
/utopia/UTPA2-700.0.x/modules/hdmi/drv/cec/include/
H A Dcec_hwreg_utility2.h245 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
246 RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1, u16Val ); } )
249 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
250 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) ; } )
253 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
254 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask); })
257 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
258 …RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) )<<1 , (RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Re…
/utopia/UTPA2-700.0.x/modules/xc/drv/ace/include/
H A Dace_hwreg_utility2.h253 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
254 RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1, u16Val ); } )
257 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
258 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) ; } )
261 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
262 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask); })
265 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
266 …RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) )<<1 , (RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Re…
/utopia/UTPA2-700.0.x/modules/pq/drv/pq/include/
H A Dhwreg_utility2.h254 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
255 RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1, u16Val ); } )
258 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
259 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) ; } )
262 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
263 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask); })
266 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
267 …RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) )<<1 , (RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Re…
/utopia/UTPA2-700.0.x/modules/xc/drv/pnl/include/
H A Dpnl_hwreg_utility2.h2394 #if (REG_MOD_BASE != 0x303200)
2397 ( { RIU_WRITE_2BYTE((REG_MOD_BASE+0xFE) << 1, ((u32Reg) >> 8) & 0x00FF ); \
2398 RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1, u16Val ); } )
2401 ( { RIU_WRITE_2BYTE((REG_MOD_BASE+0xFE) << 1, ((u32Reg) >> 8) & 0x00FF ); \
2402 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) ; } )
2405 ( { RIU_WRITE_2BYTE((REG_MOD_BASE+0xFE) << 1, ((u32Reg) >> 8) & 0x00FF ); \
2406 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask); })
2409 ( { RIU_WRITE_2BYTE((REG_MOD_BASE+0xFE) << 1, ((u32Reg) >> 8) & 0x00FF ); \
2410 …RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) )<<1 , (RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Re…
2414 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dxc_Analog_Reg.h256 #define L_BK_MOD(x) BK_REG_L(REG_MOD_BASE, x)
257 #define H_BK_MOD(x) BK_REG_H(REG_MOD_BASE, x)
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dxc_Analog_Reg.h256 #define L_BK_MOD(x) BK_REG_L(REG_MOD_BASE, x)
257 #define H_BK_MOD(x) BK_REG_H(REG_MOD_BASE, x)
/utopia/UTPA2-700.0.x/modules/wble/hal/maserati/wble/include/
H A Dwble_hwreg.h104 #define REG_MOD_BASE 0x3200UL macro
/utopia/UTPA2-700.0.x/modules/wble/hal/mooney/wble/include/
H A Dwble_hwreg.h104 #define REG_MOD_BASE 0x3200UL macro
/utopia/UTPA2-700.0.x/modules/wble/hal/maxim/wble/include/
H A Dwble_hwreg.h104 #define REG_MOD_BASE 0x3200UL macro
/utopia/UTPA2-700.0.x/modules/wble/hal/messi/wble/include/
H A Dwble_hwreg.h104 #define REG_MOD_BASE 0x3200UL macro
/utopia/UTPA2-700.0.x/modules/wble/hal/M7621/wble/include/
H A Dwble_hwreg.h104 #define REG_MOD_BASE 0x3200UL macro
/utopia/UTPA2-700.0.x/modules/wble/hal/macan/wble/include/
H A Dwble_hwreg.h104 #define REG_MOD_BASE 0x3200UL macro
/utopia/UTPA2-700.0.x/modules/wble/hal/mainz/wble/include/
H A Dwble_hwreg.h104 #define REG_MOD_BASE 0x3200UL macro
/utopia/UTPA2-700.0.x/modules/wble/hal/manhattan/wble/include/
H A Dwble_hwreg.h104 #define REG_MOD_BASE 0x3200UL macro
/utopia/UTPA2-700.0.x/modules/wble/hal/M7821/wble/include/
H A Dwble_hwreg.h104 #define REG_MOD_BASE 0x3200UL macro
/utopia/UTPA2-700.0.x/modules/wble/hal/maldives/wble/include/
H A Dwble_hwreg.h104 #define REG_MOD_BASE 0x3200 macro
/utopia/UTPA2-700.0.x/modules/wble/hal/mustang/wble/include/
H A Dwble_hwreg.h104 #define REG_MOD_BASE 0x3200 macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/cec/include/
H A Dcec_hwreg.h117 #define REG_MOD_BASE 0x103200UL macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/cec/include/
H A Dcec_hwreg.h117 #define REG_MOD_BASE 0x103200UL macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/cec/include/
H A Dcec_hwreg.h117 #define REG_MOD_BASE 0x103200UL macro

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