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Searched refs:REG_MHL_ECBUS_PHY_7F (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhwregMHL.h639 #define REG_MHL_ECBUS_PHY_7F (REG_MHL_ECBUS_PHY_BANK + 0xFE) macro
H A DhalMHL.c1467 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/
H A DhwregMHL.h639 #define REG_MHL_ECBUS_PHY_7F (REG_MHL_ECBUS_PHY_BANK + 0xFE) macro
H A DhalMHL.c1145 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhwregMHL.h639 #define REG_MHL_ECBUS_PHY_7F (REG_MHL_ECBUS_PHY_BANK + 0xFE) macro
H A DhalMHL.c1413 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/
H A DhwregMHL.h639 #define REG_MHL_ECBUS_PHY_7F (REG_MHL_ECBUS_PHY_BANK + 0xFE) macro
H A DhalMHL.c1145 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhwregMHL.h639 #define REG_MHL_ECBUS_PHY_7F (REG_MHL_ECBUS_PHY_BANK + 0xFE) macro
H A DhalMHL.c1413 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhwregMHL.h639 #define REG_MHL_ECBUS_PHY_7F (REG_MHL_ECBUS_PHY_BANK + 0xFE) macro
H A DhalMHL.c1451 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhwregMHL.h639 #define REG_MHL_ECBUS_PHY_7F (REG_MHL_ECBUS_PHY_BANK + 0xFE) macro
H A DhalMHL.c1413 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhwregMHL.h639 #define REG_MHL_ECBUS_PHY_7F (REG_MHL_ECBUS_PHY_BANK + 0xFE) macro
H A DhalMHL.c1413 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhwregMHL.h639 #define REG_MHL_ECBUS_PHY_7F (REG_MHL_ECBUS_PHY_BANK + 0xFE) macro
H A DhalMHL.c1413 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en in _mhal_mhl_ECbusInitialSetting()