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Searched refs:REG_MHL_ECBUS_PHY_72 (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhwregMHL.h626 #define REG_MHL_ECBUS_PHY_72 (REG_MHL_ECBUS_PHY_BANK + 0xE4) macro
H A DhalMHL.c1496 …W2BYTEMSK(REG_MHL_ECBUS_PHY_72, 0x0007, BMASK(15:0)); // [12:8]:reg_cr_unlock_num, clock unlock th… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/
H A DhwregMHL.h626 #define REG_MHL_ECBUS_PHY_72 (REG_MHL_ECBUS_PHY_BANK + 0xE4) macro
H A DhalMHL.c1174 …W2BYTEMSK(REG_MHL_ECBUS_PHY_72, 0x0007, BMASK(15:0)); // [12:8]:reg_cr_unlock_num, clock unlock th… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhwregMHL.h626 #define REG_MHL_ECBUS_PHY_72 (REG_MHL_ECBUS_PHY_BANK + 0xE4) macro
H A DhalMHL.c1442 …W2BYTEMSK(REG_MHL_ECBUS_PHY_72, 0x0007, BMASK(15:0)); // [12:8]:reg_cr_unlock_num, clock unlock th… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/
H A DhwregMHL.h626 #define REG_MHL_ECBUS_PHY_72 (REG_MHL_ECBUS_PHY_BANK + 0xE4) macro
H A DhalMHL.c1174 …W2BYTEMSK(REG_MHL_ECBUS_PHY_72, 0x0007, BMASK(15:0)); // [12:8]:reg_cr_unlock_num, clock unlock th… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhwregMHL.h626 #define REG_MHL_ECBUS_PHY_72 (REG_MHL_ECBUS_PHY_BANK + 0xE4) macro
H A DhalMHL.c1442 …W2BYTEMSK(REG_MHL_ECBUS_PHY_72, 0x0007, BMASK(15:0)); // [12:8]:reg_cr_unlock_num, clock unlock th… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhwregMHL.h626 #define REG_MHL_ECBUS_PHY_72 (REG_MHL_ECBUS_PHY_BANK + 0xE4) macro
H A DhalMHL.c1480 …W2BYTEMSK(REG_MHL_ECBUS_PHY_72, 0x0007, BMASK(15:0)); // [12:8]:reg_cr_unlock_num, clock unlock th… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhwregMHL.h626 #define REG_MHL_ECBUS_PHY_72 (REG_MHL_ECBUS_PHY_BANK + 0xE4) macro
H A DhalMHL.c1442 …W2BYTEMSK(REG_MHL_ECBUS_PHY_72, 0x0007, BMASK(15:0)); // [12:8]:reg_cr_unlock_num, clock unlock th… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhwregMHL.h626 #define REG_MHL_ECBUS_PHY_72 (REG_MHL_ECBUS_PHY_BANK + 0xE4) macro
H A DhalMHL.c1442 …W2BYTEMSK(REG_MHL_ECBUS_PHY_72, 0x0007, BMASK(15:0)); // [12:8]:reg_cr_unlock_num, clock unlock th… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhwregMHL.h626 #define REG_MHL_ECBUS_PHY_72 (REG_MHL_ECBUS_PHY_BANK + 0xE4) macro
H A DhalMHL.c1442 …W2BYTEMSK(REG_MHL_ECBUS_PHY_72, 0x0007, BMASK(15:0)); // [12:8]:reg_cr_unlock_num, clock unlock th… in _mhal_mhl_ECbusInitialSetting()