Searched refs:REG_MHL_ECBUS_PHY_70 (Results 1 – 18 of 18) sorted by relevance
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/ |
| H A D | hwregMHL.h | 624 #define REG_MHL_ECBUS_PHY_70 (REG_MHL_ECBUS_PHY_BANK + 0xE0) macro
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| H A D | halMHL.c | 1494 …W2BYTEMSK(REG_MHL_ECBUS_PHY_70, 0x032B, BMASK(15:0)); // [15:0]:reg_crlock_mid; the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/ |
| H A D | hwregMHL.h | 624 #define REG_MHL_ECBUS_PHY_70 (REG_MHL_ECBUS_PHY_BANK + 0xE0) macro
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| H A D | halMHL.c | 1172 …W2BYTEMSK(REG_MHL_ECBUS_PHY_70, 0x032B, BMASK(15:0)); // [15:0]:reg_crlock_mid; the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/ |
| H A D | hwregMHL.h | 624 #define REG_MHL_ECBUS_PHY_70 (REG_MHL_ECBUS_PHY_BANK + 0xE0) macro
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| H A D | halMHL.c | 1440 …W2BYTEMSK(REG_MHL_ECBUS_PHY_70, 0x032B, BMASK(15:0)); // [15:0]:reg_crlock_mid; the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/ |
| H A D | hwregMHL.h | 624 #define REG_MHL_ECBUS_PHY_70 (REG_MHL_ECBUS_PHY_BANK + 0xE0) macro
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| H A D | halMHL.c | 1172 …W2BYTEMSK(REG_MHL_ECBUS_PHY_70, 0x032B, BMASK(15:0)); // [15:0]:reg_crlock_mid; the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/ |
| H A D | hwregMHL.h | 624 #define REG_MHL_ECBUS_PHY_70 (REG_MHL_ECBUS_PHY_BANK + 0xE0) macro
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| H A D | halMHL.c | 1440 …W2BYTEMSK(REG_MHL_ECBUS_PHY_70, 0x032B, BMASK(15:0)); // [15:0]:reg_crlock_mid; the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/ |
| H A D | hwregMHL.h | 624 #define REG_MHL_ECBUS_PHY_70 (REG_MHL_ECBUS_PHY_BANK + 0xE0) macro
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| H A D | halMHL.c | 1478 …W2BYTEMSK(REG_MHL_ECBUS_PHY_70, 0x032B, BMASK(15:0)); // [15:0]:reg_crlock_mid; the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/ |
| H A D | hwregMHL.h | 624 #define REG_MHL_ECBUS_PHY_70 (REG_MHL_ECBUS_PHY_BANK + 0xE0) macro
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| H A D | halMHL.c | 1440 …W2BYTEMSK(REG_MHL_ECBUS_PHY_70, 0x032B, BMASK(15:0)); // [15:0]:reg_crlock_mid; the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/ |
| H A D | hwregMHL.h | 624 #define REG_MHL_ECBUS_PHY_70 (REG_MHL_ECBUS_PHY_BANK + 0xE0) macro
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| H A D | halMHL.c | 1440 …W2BYTEMSK(REG_MHL_ECBUS_PHY_70, 0x032B, BMASK(15:0)); // [15:0]:reg_crlock_mid; the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/ |
| H A D | hwregMHL.h | 624 #define REG_MHL_ECBUS_PHY_70 (REG_MHL_ECBUS_PHY_BANK + 0xE0) macro
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| H A D | halMHL.c | 1440 …W2BYTEMSK(REG_MHL_ECBUS_PHY_70, 0x032B, BMASK(15:0)); // [15:0]:reg_crlock_mid; the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
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