Home
last modified time | relevance | path

Searched refs:REG_MHL_ECBUS_PHY_67 (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhwregMHL.h615 #define REG_MHL_ECBUS_PHY_67 (REG_MHL_ECBUS_PHY_BANK + 0xCE) macro
H A DhalMHL.c1502 …W2BYTEMSK(REG_MHL_ECBUS_PHY_67, 0x0403, BMASK(15:0)); // [14:12]:reg_val_aft_adj_ok, [10:8]:reg_tx… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/
H A DhwregMHL.h615 #define REG_MHL_ECBUS_PHY_67 (REG_MHL_ECBUS_PHY_BANK + 0xCE) macro
H A DhalMHL.c1180 …W2BYTEMSK(REG_MHL_ECBUS_PHY_67, 0x0403, BMASK(15:0)); // [14:12]:reg_val_aft_adj_ok, [10:8]:reg_tx… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhwregMHL.h615 #define REG_MHL_ECBUS_PHY_67 (REG_MHL_ECBUS_PHY_BANK + 0xCE) macro
H A DhalMHL.c1448 …W2BYTEMSK(REG_MHL_ECBUS_PHY_67, 0x0403, BMASK(15:0)); // [14:12]:reg_val_aft_adj_ok, [10:8]:reg_tx… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/
H A DhwregMHL.h615 #define REG_MHL_ECBUS_PHY_67 (REG_MHL_ECBUS_PHY_BANK + 0xCE) macro
H A DhalMHL.c1180 …W2BYTEMSK(REG_MHL_ECBUS_PHY_67, 0x0403, BMASK(15:0)); // [14:12]:reg_val_aft_adj_ok, [10:8]:reg_tx… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhwregMHL.h615 #define REG_MHL_ECBUS_PHY_67 (REG_MHL_ECBUS_PHY_BANK + 0xCE) macro
H A DhalMHL.c1448 …W2BYTEMSK(REG_MHL_ECBUS_PHY_67, 0x0403, BMASK(15:0)); // [14:12]:reg_val_aft_adj_ok, [10:8]:reg_tx… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhwregMHL.h615 #define REG_MHL_ECBUS_PHY_67 (REG_MHL_ECBUS_PHY_BANK + 0xCE) macro
H A DhalMHL.c1486 …W2BYTEMSK(REG_MHL_ECBUS_PHY_67, 0x0403, BMASK(15:0)); // [14:12]:reg_val_aft_adj_ok, [10:8]:reg_tx… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhwregMHL.h615 #define REG_MHL_ECBUS_PHY_67 (REG_MHL_ECBUS_PHY_BANK + 0xCE) macro
H A DhalMHL.c1448 …W2BYTEMSK(REG_MHL_ECBUS_PHY_67, 0x0403, BMASK(15:0)); // [14:12]:reg_val_aft_adj_ok, [10:8]:reg_tx… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhwregMHL.h615 #define REG_MHL_ECBUS_PHY_67 (REG_MHL_ECBUS_PHY_BANK + 0xCE) macro
H A DhalMHL.c1448 …W2BYTEMSK(REG_MHL_ECBUS_PHY_67, 0x0403, BMASK(15:0)); // [14:12]:reg_val_aft_adj_ok, [10:8]:reg_tx… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhwregMHL.h615 #define REG_MHL_ECBUS_PHY_67 (REG_MHL_ECBUS_PHY_BANK + 0xCE) macro
H A DhalMHL.c1448 …W2BYTEMSK(REG_MHL_ECBUS_PHY_67, 0x0403, BMASK(15:0)); // [14:12]:reg_val_aft_adj_ok, [10:8]:reg_tx… in _mhal_mhl_ECbusInitialSetting()