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Searched refs:REG_MHL_ECBUS_PHY_57 (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/
H A DhalMHL.c1151 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, 0x06, BMASK(3:0)); // [11:8]: in _mhal_mhl_ECbusInitialSetting()
1268 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()
H A DhwregMHL.h599 #define REG_MHL_ECBUS_PHY_57 (REG_MHL_ECBUS_PHY_BANK + 0xAE) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/
H A DhalMHL.c1151 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, 0x06, BMASK(3:0)); // [11:8]: in _mhal_mhl_ECbusInitialSetting()
1268 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()
H A DhwregMHL.h599 #define REG_MHL_ECBUS_PHY_57 (REG_MHL_ECBUS_PHY_BANK + 0xAE) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhwregMHL.h599 #define REG_MHL_ECBUS_PHY_57 (REG_MHL_ECBUS_PHY_BANK + 0xAE) macro
H A DhalMHL.c1473 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, 0x06, BMASK(3:0)); // [11:8]: in _mhal_mhl_ECbusInitialSetting()
1590 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhwregMHL.h599 #define REG_MHL_ECBUS_PHY_57 (REG_MHL_ECBUS_PHY_BANK + 0xAE) macro
H A DhalMHL.c1419 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, 0x700, BMASK(11:8)); // [11:8]: in _mhal_mhl_ECbusInitialSetting()
1536 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhwregMHL.h599 #define REG_MHL_ECBUS_PHY_57 (REG_MHL_ECBUS_PHY_BANK + 0xAE) macro
H A DhalMHL.c1419 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, 0x700, BMASK(11:8)); // [11:8]: in _mhal_mhl_ECbusInitialSetting()
1536 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhwregMHL.h599 #define REG_MHL_ECBUS_PHY_57 (REG_MHL_ECBUS_PHY_BANK + 0xAE) macro
H A DhalMHL.c1457 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, 0x06, BMASK(3:0)); // [11:8]: in _mhal_mhl_ECbusInitialSetting()
1574 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhwregMHL.h599 #define REG_MHL_ECBUS_PHY_57 (REG_MHL_ECBUS_PHY_BANK + 0xAE) macro
H A DhalMHL.c1419 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, 0x700, BMASK(11:8)); // [11:8]: in _mhal_mhl_ECbusInitialSetting()
1536 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhwregMHL.h599 #define REG_MHL_ECBUS_PHY_57 (REG_MHL_ECBUS_PHY_BANK + 0xAE) macro
H A DhalMHL.c1419 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, 0x700, BMASK(11:8)); // [11:8]: in _mhal_mhl_ECbusInitialSetting()
1536 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhwregMHL.h599 #define REG_MHL_ECBUS_PHY_57 (REG_MHL_ECBUS_PHY_BANK + 0xAE) macro
H A DhalMHL.c1419 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, 0x700, BMASK(11:8)); // [11:8]: in _mhal_mhl_ECbusInitialSetting()
1536 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()