| /utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/ |
| H A D | halMHL.c | 1138 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, 0x0F00, BMASK(15:0)); // [7:4]:reg_ecbss_afe_tx_dri_step in _mhal_mhl_ECbusInitialSetting()
1295 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux in _mhal_mhl_ECbusDmuxEnable()
|
| H A D | hwregMHL.h | 591 #define REG_MHL_ECBUS_PHY_4F (REG_MHL_ECBUS_PHY_BANK + 0x9E) macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/ |
| H A D | halMHL.c | 1138 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, 0x0F00, BMASK(15:0)); // [7:4]:reg_ecbss_afe_tx_dri_step in _mhal_mhl_ECbusInitialSetting()
1295 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux in _mhal_mhl_ECbusDmuxEnable()
|
| H A D | hwregMHL.h | 591 #define REG_MHL_ECBUS_PHY_4F (REG_MHL_ECBUS_PHY_BANK + 0x9E) macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/ |
| H A D | hwregMHL.h | 591 #define REG_MHL_ECBUS_PHY_4F (REG_MHL_ECBUS_PHY_BANK + 0x9E) macro
|
| H A D | halMHL.c | 1460 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, 0x00F0, BMASK(15:0)); // [7:4]:reg_ecbss_afe_tx_dri_step in _mhal_mhl_ECbusInitialSetting()
1617 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux in _mhal_mhl_ECbusDmuxEnable()
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/ |
| H A D | hwregMHL.h | 591 #define REG_MHL_ECBUS_PHY_4F (REG_MHL_ECBUS_PHY_BANK + 0x9E) macro
|
| H A D | halMHL.c | 1406 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, 0x00F0, BMASK(15:0)); // [7:4]:reg_ecbss_afe_tx_dri_step in _mhal_mhl_ECbusInitialSetting()
1623 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux in _mhal_mhl_ECbusDmuxEnable()
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/ |
| H A D | hwregMHL.h | 591 #define REG_MHL_ECBUS_PHY_4F (REG_MHL_ECBUS_PHY_BANK + 0x9E) macro
|
| H A D | halMHL.c | 1406 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, 0x00F0, BMASK(15:0)); // [7:4]:reg_ecbss_afe_tx_dri_step in _mhal_mhl_ECbusInitialSetting()
1623 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux in _mhal_mhl_ECbusDmuxEnable()
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/ |
| H A D | hwregMHL.h | 591 #define REG_MHL_ECBUS_PHY_4F (REG_MHL_ECBUS_PHY_BANK + 0x9E) macro
|
| H A D | halMHL.c | 1444 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, 0x00F0, BMASK(15:0)); // [7:4]:reg_ecbss_afe_tx_dri_step in _mhal_mhl_ECbusInitialSetting()
1601 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux in _mhal_mhl_ECbusDmuxEnable()
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/ |
| H A D | hwregMHL.h | 591 #define REG_MHL_ECBUS_PHY_4F (REG_MHL_ECBUS_PHY_BANK + 0x9E) macro
|
| H A D | halMHL.c | 1406 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, 0x00F0, BMASK(15:0)); // [7:4]:reg_ecbss_afe_tx_dri_step in _mhal_mhl_ECbusInitialSetting()
1623 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux in _mhal_mhl_ECbusDmuxEnable()
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/ |
| H A D | hwregMHL.h | 591 #define REG_MHL_ECBUS_PHY_4F (REG_MHL_ECBUS_PHY_BANK + 0x9E) macro
|
| H A D | halMHL.c | 1406 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, 0x00F0, BMASK(15:0)); // [7:4]:reg_ecbss_afe_tx_dri_step in _mhal_mhl_ECbusInitialSetting()
1623 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux in _mhal_mhl_ECbusDmuxEnable()
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/ |
| H A D | hwregMHL.h | 591 #define REG_MHL_ECBUS_PHY_4F (REG_MHL_ECBUS_PHY_BANK + 0x9E) macro
|
| H A D | halMHL.c | 1406 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, 0x00F0, BMASK(15:0)); // [7:4]:reg_ecbss_afe_tx_dri_step in _mhal_mhl_ECbusInitialSetting()
1623 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux in _mhal_mhl_ECbusDmuxEnable()
|