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Searched refs:REG_MHL_ECBUS_PHY_4B (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhalMHL.c1404 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusInitialSetting()
1457 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1539 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1569 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1572 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(14), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1582 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1588 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1602 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13), BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1605 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1827 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:12), BMASK(14:12)); // delay in _mhal_mhl_ECbusModeUpProc()
H A DhwregMHL.h587 #define REG_MHL_ECBUS_PHY_4B (REG_MHL_ECBUS_PHY_BANK + 0x96) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhalMHL.c1404 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusInitialSetting()
1457 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1539 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1569 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1572 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(14), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1582 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1588 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1602 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13), BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1605 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1827 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:12), BMASK(14:12)); // delay in _mhal_mhl_ECbusModeUpProc()
H A DhwregMHL.h587 #define REG_MHL_ECBUS_PHY_4B (REG_MHL_ECBUS_PHY_BANK + 0x96) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhalMHL.c1404 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusInitialSetting()
1457 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1539 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1569 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1572 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(14), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1582 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1588 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1602 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13), BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1605 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1827 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:12), BMASK(14:12)); // delay in _mhal_mhl_ECbusModeUpProc()
H A DhwregMHL.h587 #define REG_MHL_ECBUS_PHY_4B (REG_MHL_ECBUS_PHY_BANK + 0x96) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhalMHL.c1404 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusInitialSetting()
1457 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1539 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1569 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1572 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(14), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1582 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1588 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1602 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13), BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1605 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1827 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:12), BMASK(14:12)); // delay in _mhal_mhl_ECbusModeUpProc()
H A DhwregMHL.h587 #define REG_MHL_ECBUS_PHY_4B (REG_MHL_ECBUS_PHY_BANK + 0x96) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhalMHL.c1404 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusInitialSetting()
1457 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1539 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1569 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1572 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(14), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1582 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1588 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1602 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13), BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1605 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1827 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:12), BMASK(14:12)); // delay in _mhal_mhl_ECbusModeUpProc()
H A DhwregMHL.h587 #define REG_MHL_ECBUS_PHY_4B (REG_MHL_ECBUS_PHY_BANK + 0x96) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/
H A DhalMHL.c1136 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusInitialSetting()
1189 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1271 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1456 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13)| BIT(12), BMASK(14:12)); // delay in _mhal_mhl_ECbusStateChangeProc()
1486 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:12), BMASK(14:12)); // delay in _mhal_mhl_ECbusModeUpProc()
H A DhwregMHL.h587 #define REG_MHL_ECBUS_PHY_4B (REG_MHL_ECBUS_PHY_BANK + 0x96) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/
H A DhalMHL.c1136 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusInitialSetting()
1189 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1271 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1456 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13)| BIT(12), BMASK(14:12)); // delay in _mhal_mhl_ECbusStateChangeProc()
1486 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:12), BMASK(14:12)); // delay in _mhal_mhl_ECbusModeUpProc()
H A DhwregMHL.h587 #define REG_MHL_ECBUS_PHY_4B (REG_MHL_ECBUS_PHY_BANK + 0x96) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhalMHL.c1442 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusInitialSetting()
1495 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1577 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1768 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13)| BIT(12), BMASK(14:12)); // delay in _mhal_mhl_ECbusStateChangeProc()
1798 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:12), BMASK(14:12)); // delay in _mhal_mhl_ECbusModeUpProc()
H A DhwregMHL.h587 #define REG_MHL_ECBUS_PHY_4B (REG_MHL_ECBUS_PHY_BANK + 0x96) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhalMHL.c1458 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13)); in _mhal_mhl_ECbusInitialSetting()
1511 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1593 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1784 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13)| BIT(12), BMASK(14:12)); // delay in _mhal_mhl_ECbusStateChangeProc()
1814 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:12), BMASK(14:12)); // delay in _mhal_mhl_ECbusModeUpProc()
H A DhwregMHL.h587 #define REG_MHL_ECBUS_PHY_4B (REG_MHL_ECBUS_PHY_BANK + 0x96) macro