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Searched refs:REG_MHL_ECBUS_34 (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/
H A DhalMHL.c1220 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear in _mhal_mhl_SetECbusStateChangeInterrupt()
1236 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear in _mhal_mhl_SetEMSCReceiveInterrupt()
1436 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4] in _mhal_mhl_ECbusStateChangeProc()
1480 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1481 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
3057 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); in mhal_mhl_GetECbusStateChangeFlag()
3081 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); in mhal_mhl_GetEMSCReceiveFlag()
3103 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear in mhal_mhl_GetEMSCSendStatus()
3109 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear in mhal_mhl_GetEMSCSendStatus()
3924 W2BYTE(REG_MHL_ECBUS_34, 0xFFFF); in mhal_mhl_ECbusEventProc()
H A DhwregMHL.h432 #define REG_MHL_ECBUS_34 (REG_MHL_ECBUS_BANK + 0x68) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/
H A DhalMHL.c1220 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear in _mhal_mhl_SetECbusStateChangeInterrupt()
1236 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear in _mhal_mhl_SetEMSCReceiveInterrupt()
1436 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4] in _mhal_mhl_ECbusStateChangeProc()
1480 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1481 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
3057 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); in mhal_mhl_GetECbusStateChangeFlag()
3081 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); in mhal_mhl_GetEMSCReceiveFlag()
3103 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear in mhal_mhl_GetEMSCSendStatus()
3109 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear in mhal_mhl_GetEMSCSendStatus()
3924 W2BYTE(REG_MHL_ECBUS_34, 0xFFFF); in mhal_mhl_ECbusEventProc()
H A DhwregMHL.h432 #define REG_MHL_ECBUS_34 (REG_MHL_ECBUS_BANK + 0x68) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhalMHL.c1526 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear in _mhal_mhl_SetECbusStateChangeInterrupt()
1542 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear in _mhal_mhl_SetEMSCReceiveInterrupt()
1748 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4] in _mhal_mhl_ECbusStateChangeProc()
1792 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1793 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
3514 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); in mhal_mhl_GetECbusStateChangeFlag()
3538 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); in mhal_mhl_GetEMSCReceiveFlag()
3560 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear in mhal_mhl_GetEMSCSendStatus()
3566 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear in mhal_mhl_GetEMSCSendStatus()
4366 W2BYTE(REG_MHL_ECBUS_34, 0xFFFF); in mhal_mhl_ECbusEventProc()
H A DhwregMHL.h432 #define REG_MHL_ECBUS_34 (REG_MHL_ECBUS_BANK + 0x68) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhalMHL.c1542 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear in _mhal_mhl_SetECbusStateChangeInterrupt()
1558 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear in _mhal_mhl_SetEMSCReceiveInterrupt()
1764 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4] in _mhal_mhl_ECbusStateChangeProc()
1808 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1809 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
3538 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); in mhal_mhl_GetECbusStateChangeFlag()
3562 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); in mhal_mhl_GetEMSCReceiveFlag()
3584 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear in mhal_mhl_GetEMSCSendStatus()
3590 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear in mhal_mhl_GetEMSCSendStatus()
4390 W2BYTE(REG_MHL_ECBUS_34, 0xFFFF); in mhal_mhl_ECbusEventProc()
H A DhwregMHL.h432 #define REG_MHL_ECBUS_34 (REG_MHL_ECBUS_BANK + 0x68) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhalMHL.c1488 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear in _mhal_mhl_SetECbusStateChangeInterrupt()
1504 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear in _mhal_mhl_SetEMSCReceiveInterrupt()
1821 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1822 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
4049 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); in mhal_mhl_GetECbusStateChangeFlag()
4076 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); in mhal_mhl_GetEMSCReceiveFlag()
4098 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear in mhal_mhl_GetEMSCSendStatus()
4104 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear in mhal_mhl_GetEMSCSendStatus()
4831 W2BYTE(REG_MHL_ECBUS_34, 0xFFFF); in mhal_mhl_ECbusEventProc()
H A DhwregMHL.h432 #define REG_MHL_ECBUS_34 (REG_MHL_ECBUS_BANK + 0x68) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhalMHL.c1488 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear in _mhal_mhl_SetECbusStateChangeInterrupt()
1504 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear in _mhal_mhl_SetEMSCReceiveInterrupt()
1821 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1822 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
4049 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); in mhal_mhl_GetECbusStateChangeFlag()
4076 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); in mhal_mhl_GetEMSCReceiveFlag()
4098 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear in mhal_mhl_GetEMSCSendStatus()
4104 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear in mhal_mhl_GetEMSCSendStatus()
4831 W2BYTE(REG_MHL_ECBUS_34, 0xFFFF); in mhal_mhl_ECbusEventProc()
H A DhwregMHL.h432 #define REG_MHL_ECBUS_34 (REG_MHL_ECBUS_BANK + 0x68) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhalMHL.c1488 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear in _mhal_mhl_SetECbusStateChangeInterrupt()
1504 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear in _mhal_mhl_SetEMSCReceiveInterrupt()
1821 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1822 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
4049 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); in mhal_mhl_GetECbusStateChangeFlag()
4076 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); in mhal_mhl_GetEMSCReceiveFlag()
4098 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear in mhal_mhl_GetEMSCSendStatus()
4104 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear in mhal_mhl_GetEMSCSendStatus()
4831 W2BYTE(REG_MHL_ECBUS_34, 0xFFFF); in mhal_mhl_ECbusEventProc()
H A DhwregMHL.h432 #define REG_MHL_ECBUS_34 (REG_MHL_ECBUS_BANK + 0x68) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhalMHL.c1488 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear in _mhal_mhl_SetECbusStateChangeInterrupt()
1504 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear in _mhal_mhl_SetEMSCReceiveInterrupt()
1821 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1822 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
4049 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); in mhal_mhl_GetECbusStateChangeFlag()
4076 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); in mhal_mhl_GetEMSCReceiveFlag()
4098 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear in mhal_mhl_GetEMSCSendStatus()
4104 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear in mhal_mhl_GetEMSCSendStatus()
4831 W2BYTE(REG_MHL_ECBUS_34, 0xFFFF); in mhal_mhl_ECbusEventProc()
H A DhwregMHL.h432 #define REG_MHL_ECBUS_34 (REG_MHL_ECBUS_BANK + 0x68) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhalMHL.c1488 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear in _mhal_mhl_SetECbusStateChangeInterrupt()
1504 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear in _mhal_mhl_SetEMSCReceiveInterrupt()
1821 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1822 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
4049 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); in mhal_mhl_GetECbusStateChangeFlag()
4076 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); in mhal_mhl_GetEMSCReceiveFlag()
4098 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear in mhal_mhl_GetEMSCSendStatus()
4104 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear in mhal_mhl_GetEMSCSendStatus()
4831 W2BYTE(REG_MHL_ECBUS_34, 0xFFFF); in mhal_mhl_ECbusEventProc()
H A DhwregMHL.h432 #define REG_MHL_ECBUS_34 (REG_MHL_ECBUS_BANK + 0x68) macro