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Searched refs:REG_IRQHYP_MASK_H (Results 1 – 10 of 10) sorted by relevance

/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DhalCHIP.c517 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
543 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_EnableIRQ()
596 IRQHYP_REG(REG_IRQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
622 IRQHYP_REG(REG_IRQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_DisableIRQ()
1653 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1679 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_EnableIRQ()
1732 IRQHYP_REG(REG_IRQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1758 IRQHYP_REG(REG_IRQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h178 #define REG_IRQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0015) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DhalCHIP.c517 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
543 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_EnableIRQ()
596 IRQHYP_REG(REG_IRQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
622 IRQHYP_REG(REG_IRQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_DisableIRQ()
1653 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1679 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_EnableIRQ()
1732 IRQHYP_REG(REG_IRQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1758 IRQHYP_REG(REG_IRQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h178 #define REG_IRQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0015) macro
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DhalCHIP.c517 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
543 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_EnableIRQ()
596 IRQHYP_REG(REG_IRQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
622 IRQHYP_REG(REG_IRQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_DisableIRQ()
1640 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1666 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_EnableIRQ()
1719 IRQHYP_REG(REG_IRQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1745 IRQHYP_REG(REG_IRQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h178 #define REG_IRQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0015) macro
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DhalCHIP.c517 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
543 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_EnableIRQ()
596 IRQHYP_REG(REG_IRQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
622 IRQHYP_REG(REG_IRQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_DisableIRQ()
1653 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1679 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_EnableIRQ()
1732 IRQHYP_REG(REG_IRQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1758 IRQHYP_REG(REG_IRQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h178 #define REG_IRQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0015) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DhalCHIP.c517 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
543 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_EnableIRQ()
596 IRQHYP_REG(REG_IRQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
622 IRQHYP_REG(REG_IRQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_DisableIRQ()
1653 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1679 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_EnableIRQ()
1732 IRQHYP_REG(REG_IRQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1758 IRQHYP_REG(REG_IRQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQHYPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h178 #define REG_IRQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0015) macro