Home
last modified time | relevance | path

Searched refs:REG_HWI2C_INT_CTL (Results 1 – 25 of 30) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/hwi2c/hal/kano/hwi2c/
H A DhalHWI2C.c177 0x0, HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL) );
1681 return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; in HAL_HWI2C_Is_INT()
1699 return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); in HAL_HWI2C_Clear_INT()
H A DregHWI2C.h188 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/curry/hwi2c/
H A DhalHWI2C.c177 0x0, HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL) );
1681 return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; in HAL_HWI2C_Is_INT()
1699 return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); in HAL_HWI2C_Clear_INT()
H A DregHWI2C.h188 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6/hwi2c/
H A DhalHWI2C.c177 0x0, HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL) );
1681 return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; in HAL_HWI2C_Is_INT()
1699 return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); in HAL_HWI2C_Clear_INT()
H A DregHWI2C.h188 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6lite/hwi2c/
H A DhalHWI2C.c177 0x0, HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL) );
1681 return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; in HAL_HWI2C_Is_INT()
1699 return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); in HAL_HWI2C_Clear_INT()
H A DregHWI2C.h188 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maldives/hwi2c/
H A DhalHWI2C.c1432 return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u32PortOffset) & _INT_CTL) ? TRUE : FALSE; in HAL_HWI2C_Is_INT()
1446 return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u32PortOffset, _INT_CTL, TRUE); in HAL_HWI2C_Clear_INT()
H A DregHWI2C.h183 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mainz/hwi2c/
H A DhalHWI2C.c1386 return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u32PortOffset) & _INT_CTL) ? TRUE : FALSE; in HAL_HWI2C_Is_INT()
1400 return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u32PortOffset, _INT_CTL, TRUE); in HAL_HWI2C_Clear_INT()
H A DregHWI2C.h163 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/macan/hwi2c/
H A DhalHWI2C.c1430 return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u32PortOffset) & _INT_CTL) ? TRUE : FALSE; in HAL_HWI2C_Is_INT()
1444 return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u32PortOffset, _INT_CTL, TRUE); in HAL_HWI2C_Clear_INT()
H A DregHWI2C.h185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mustang/hwi2c/
H A DhalHWI2C.c1432 return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u32PortOffset) & _INT_CTL) ? TRUE : FALSE; in HAL_HWI2C_Is_INT()
1446 return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u32PortOffset, _INT_CTL, TRUE); in HAL_HWI2C_Clear_INT()
H A DregHWI2C.h183 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/messi/hwi2c/
H A DhalHWI2C.c1432 return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u32PortOffset) & _INT_CTL) ? TRUE : FALSE; in HAL_HWI2C_Is_INT()
1446 return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u32PortOffset, _INT_CTL, TRUE); in HAL_HWI2C_Clear_INT()
H A DregHWI2C.h185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mooney/hwi2c/
H A DhalHWI2C.c1430 return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u32PortOffset) & _INT_CTL) ? TRUE : FALSE; in HAL_HWI2C_Is_INT()
1444 return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u32PortOffset, _INT_CTL, TRUE); in HAL_HWI2C_Clear_INT()
H A DregHWI2C.h185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/manhattan/hwi2c/
H A DregHWI2C.h185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7821/hwi2c/
H A DregHWI2C.h185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maserati/hwi2c/
H A DregHWI2C.h185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7621/hwi2c/
H A DregHWI2C.h185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maxim/hwi2c/
H A DregHWI2C.h185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) macro

12