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Searched refs:REG_HDMI_DUAL_0_67_L (Results 1 – 25 of 26) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c2049 W2BYTEMSK(REG_HDMI_DUAL_0_67_L, BIT(8), BIT(8)); // reg_cts_div2_en in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c2785 W2BYTEMSK(REG_HDMI_DUAL_0_67_L, BIT(8), BIT(8)); // reg_cts_div2_en in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c4266 W2BYTEMSK(REG_HDMI_DUAL_0_67_L, BIT(8), BIT(8)); // reg_cts_div2_en in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c4375 W2BYTEMSK(REG_HDMI_DUAL_0_67_L, BIT(8), BIT(8)); // reg_cts_div2_en in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c4381 W2BYTEMSK(REG_HDMI_DUAL_0_67_L, BIT(8), BIT(8)); // reg_cts_div2_en in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c4375 W2BYTEMSK(REG_HDMI_DUAL_0_67_L, BIT(8), BIT(8)); // reg_cts_div2_en in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c4325 W2BYTEMSK(REG_HDMI_DUAL_0_67_L, BIT(8), BIT(8)); // reg_cts_div2_en in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c4381 W2BYTEMSK(REG_HDMI_DUAL_0_67_L, BIT(8), BIT(8)); // reg_cts_div2_en in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c4949 W2BYTEMSK(REG_HDMI_DUAL_0_67_L, BIT(8), BIT(8)); // reg_cts_div2_en in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c4952 W2BYTEMSK(REG_HDMI_DUAL_0_67_L, BIT(8), BIT(8)); // reg_cts_div2_en in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c4525 W2BYTEMSK(REG_HDMI_DUAL_0_67_L +usHDMIBankOffset, BIT(8), BIT(8)); // reg_cts_div2_en in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c4955 W2BYTEMSK(REG_HDMI_DUAL_0_67_L, BIT(8), BIT(8)); // reg_cts_div2_en in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c4525 W2BYTEMSK(REG_HDMI_DUAL_0_67_L +usHDMIBankOffset, BIT(8), BIT(8)); // reg_cts_div2_en in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h5915 #define REG_HDMI_DUAL_0_67_L (REG_HDMI_DUAL_0_BASE + 0xCE) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h5917 #define REG_HDMI_DUAL_0_67_L (REG_HDMI_DUAL_0_BASE + 0xCE) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h5907 #define REG_HDMI_DUAL_0_67_L (REG_HDMI_DUAL_0_BASE + 0xCE) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h5917 #define REG_HDMI_DUAL_0_67_L (REG_HDMI_DUAL_0_BASE + 0xCE) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h5907 #define REG_HDMI_DUAL_0_67_L (REG_HDMI_DUAL_0_BASE + 0xCE) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h5917 #define REG_HDMI_DUAL_0_67_L (REG_HDMI_DUAL_0_BASE + 0xCE) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h5917 #define REG_HDMI_DUAL_0_67_L (REG_HDMI_DUAL_0_BASE + 0xCE) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h5907 #define REG_HDMI_DUAL_0_67_L (REG_HDMI_DUAL_0_BASE + 0xCE) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h5908 #define REG_HDMI_DUAL_0_67_L (REG_HDMI_DUAL_0_BASE + 0xCE) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h5907 #define REG_HDMI_DUAL_0_67_L (REG_HDMI_DUAL_0_BASE + 0xCE) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h5915 #define REG_HDMI_DUAL_0_67_L (REG_HDMI_DUAL_0_BASE + 0xCE) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h5915 #define REG_HDMI_DUAL_0_67_L (REG_HDMI_DUAL_0_BASE + 0xCE) macro

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