| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 1613 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BIT(11), BIT(11)); // clear interrupt Dolby EDR Valid in _Hal_tmds_ClearEDRVaildFlag()
1614 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BIT(11)); in _Hal_tmds_ClearEDRVaildFlag()
2780 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BMASK(15:8), BMASK(15:8)); // HDMI2 interrupt clear in Hal_HDMI_init()
2781 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BMASK(15:8)); in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 2732 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BIT(11), BIT(11)); // clear interrupt Dolby EDR Valid in _Hal_tmds_ClearEDRVaildFlag()
2733 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BIT(11)); in _Hal_tmds_ClearEDRVaildFlag()
4261 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BMASK(15:8), BMASK(15:8)); // HDMI2 interrupt clear in Hal_HDMI_init()
4262 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BMASK(15:8)); in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 2769 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BIT(11), BIT(11)); // clear interrupt Dolby EDR Valid in _Hal_tmds_ClearEDRVaildFlag()
2770 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BIT(11)); in _Hal_tmds_ClearEDRVaildFlag()
4370 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BMASK(15:8), BMASK(15:8)); // HDMI2 interrupt clear in Hal_HDMI_init()
4371 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BMASK(15:8)); in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 2769 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BIT(11), BIT(11)); // clear interrupt Dolby EDR Valid in _Hal_tmds_ClearEDRVaildFlag()
2770 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BIT(11)); in _Hal_tmds_ClearEDRVaildFlag()
4370 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BMASK(15:8), BMASK(15:8)); // HDMI2 interrupt clear in Hal_HDMI_init()
4371 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BMASK(15:8)); in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 2761 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BIT(11), BIT(11)); // clear interrupt Dolby EDR Valid in _Hal_tmds_ClearEDRVaildFlag()
2762 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BIT(11)); in _Hal_tmds_ClearEDRVaildFlag()
4944 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BMASK(15:8), BMASK(15:8)); // HDMI2 interrupt clear in Hal_HDMI_init()
4945 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BMASK(15:8)); in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 2763 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BIT(11), BIT(11)); // clear interrupt Dolby EDR Valid in _Hal_tmds_ClearEDRVaildFlag()
2764 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BIT(11)); in _Hal_tmds_ClearEDRVaildFlag()
4947 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BMASK(15:8), BMASK(15:8)); // HDMI2 interrupt clear in Hal_HDMI_init()
4948 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BMASK(15:8)); in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 2929 …W2BYTEMSK(REG_HDMI2_DUAL_0_27_L +usHDMIBankOffset, BIT(11), BIT(11)); // clear interrupt Dolby EDR… in _Hal_tmds_ClearEDRVaildFlag()
2930 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L +usHDMIBankOffset, 0, BIT(11)); in _Hal_tmds_ClearEDRVaildFlag()
4520 …W2BYTEMSK(REG_HDMI2_DUAL_0_27_L +usHDMIBankOffset, BMASK(15:8), BMASK(15:8)); // HDMI2 interrupt c… in Hal_HDMI_init()
4521 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L +usHDMIBankOffset, 0, BMASK(15:8)); in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 2763 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BIT(11), BIT(11)); // clear interrupt Dolby EDR Valid in _Hal_tmds_ClearEDRVaildFlag()
2764 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BIT(11)); in _Hal_tmds_ClearEDRVaildFlag()
4950 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BMASK(15:8), BMASK(15:8)); // HDMI2 interrupt clear in Hal_HDMI_init()
4951 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BMASK(15:8)); in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 2929 …W2BYTEMSK(REG_HDMI2_DUAL_0_27_L +usHDMIBankOffset, BIT(11), BIT(11)); // clear interrupt Dolby EDR… in _Hal_tmds_ClearEDRVaildFlag()
2930 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L +usHDMIBankOffset, 0, BIT(11)); in _Hal_tmds_ClearEDRVaildFlag()
4520 …W2BYTEMSK(REG_HDMI2_DUAL_0_27_L +usHDMIBankOffset, BMASK(15:8), BMASK(15:8)); // HDMI2 interrupt c… in Hal_HDMI_init()
4521 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L +usHDMIBankOffset, 0, BMASK(15:8)); in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 2044 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BMASK(15:8), BMASK(15:8)); // HDMI2 interrupt clear in Hal_HDMI_init()
2045 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BMASK(15:8)); in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 4376 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BMASK(15:8), BMASK(15:8)); // HDMI2 interrupt clear in Hal_HDMI_init()
4377 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BMASK(15:8)); in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 4320 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BMASK(15:8), BMASK(15:8)); // HDMI2 interrupt clear in Hal_HDMI_init()
4321 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BMASK(15:8)); in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 4376 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, BMASK(15:8), BMASK(15:8)); // HDMI2 interrupt clear in Hal_HDMI_init()
4377 W2BYTEMSK(REG_HDMI2_DUAL_0_27_L, 0, BMASK(15:8)); in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 6045 #define REG_HDMI2_DUAL_0_27_L (REG_HDMI2_DUAL_0_BASE + 0x4E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 6047 #define REG_HDMI2_DUAL_0_27_L (REG_HDMI2_DUAL_0_BASE + 0x4E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 6037 #define REG_HDMI2_DUAL_0_27_L (REG_HDMI2_DUAL_0_BASE + 0x4E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 6047 #define REG_HDMI2_DUAL_0_27_L (REG_HDMI2_DUAL_0_BASE + 0x4E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 6037 #define REG_HDMI2_DUAL_0_27_L (REG_HDMI2_DUAL_0_BASE + 0x4E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 6047 #define REG_HDMI2_DUAL_0_27_L (REG_HDMI2_DUAL_0_BASE + 0x4E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 6047 #define REG_HDMI2_DUAL_0_27_L (REG_HDMI2_DUAL_0_BASE + 0x4E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 6037 #define REG_HDMI2_DUAL_0_27_L (REG_HDMI2_DUAL_0_BASE + 0x4E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 6038 #define REG_HDMI2_DUAL_0_27_L (REG_HDMI2_DUAL_0_BASE + 0x4E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 6037 #define REG_HDMI2_DUAL_0_27_L (REG_HDMI2_DUAL_0_BASE + 0x4E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 6045 #define REG_HDMI2_DUAL_0_27_L (REG_HDMI2_DUAL_0_BASE + 0x4E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 6045 #define REG_HDMI2_DUAL_0_27_L (REG_HDMI2_DUAL_0_BASE + 0x4E) macro
|