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Searched refs:REG_HDMI2_DUAL_0_20_L (Results 1 – 25 of 26) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c2848 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(0)); // Disable bypass, 422to444 at HDMI in _Hal_tmds_Bypass422to444()
2852 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, BIT(0), BIT(0)); // bypass, 422to444 at scaler in _Hal_tmds_Bypass422to444()
5812 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(5)); // [5]: 0: WR_Clock_Freq in Hal_HDMI_AVG_ScaleringDown()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c2876 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(0)); // Disable bypass, 422to444 at HDMI in _Hal_tmds_Bypass422to444()
2880 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, BIT(0), BIT(0)); // bypass, 422to444 at scaler in _Hal_tmds_Bypass422to444()
6515 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(5)); // [5]: 0: WR_Clock_Freq in Hal_HDMI_AVG_ScaleringDown()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c2879 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(0)); // Disable bypass, 422to444 at HDMI in _Hal_tmds_Bypass422to444()
2883 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, BIT(0), BIT(0)); // bypass, 422to444 at scaler in _Hal_tmds_Bypass422to444()
6518 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(5)); // [5]: 0: WR_Clock_Freq in Hal_HDMI_AVG_ScaleringDown()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c3050 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(0)); // Disable bypass, 422to444 at HDMI in _Hal_tmds_Bypass422to444()
3054 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, BIT(0), BIT(0)); // bypass, 422to444 at scaler in _Hal_tmds_Bypass422to444()
6290 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L +usHDMIBankOffset, 0, BIT(5)); // [5]: 0: WR_Clock_Freq in Hal_HDMI_AVG_ScaleringDown()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c2879 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(0)); // Disable bypass, 422to444 at HDMI in _Hal_tmds_Bypass422to444()
2883 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, BIT(0), BIT(0)); // bypass, 422to444 at scaler in _Hal_tmds_Bypass422to444()
6521 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(5)); // [5]: 0: WR_Clock_Freq in Hal_HDMI_AVG_ScaleringDown()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c3050 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(0)); // Disable bypass, 422to444 at HDMI in _Hal_tmds_Bypass422to444()
3054 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, BIT(0), BIT(0)); // bypass, 422to444 at scaler in _Hal_tmds_Bypass422to444()
6290 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L +usHDMIBankOffset, 0, BIT(5)); // [5]: 0: WR_Clock_Freq in Hal_HDMI_AVG_ScaleringDown()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c1688 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(0)); // Disable bypass, 422to444 at HDMI in _Hal_tmds_Bypass422to444()
4087 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, btrue, BIT(0)); in Hal_HDMI_Set_YUV422to444_Bypass()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c2885 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(0)); // Disable bypass, 422to444 at HDMI in _Hal_tmds_Bypass422to444()
5887 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(5)); // [5]: 0: WR_Clock_Freq in Hal_HDMI_AVG_ScaleringDown()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c4468 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(0)); // Disable bypass in Hal_HDMI_init()
5927 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(5)); // [5]: 0: WR_Clock_Freq in Hal_HDMI_AVG_ScaleringDown()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c2885 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(0)); // Disable bypass, 422to444 at HDMI in _Hal_tmds_Bypass422to444()
5887 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(5)); // [5]: 0: WR_Clock_Freq in Hal_HDMI_AVG_ScaleringDown()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c4406 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(0)); // Disable bypass in Hal_HDMI_init()
5927 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(5)); // [5]: 0: WR_Clock_Freq in Hal_HDMI_AVG_ScaleringDown()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c4468 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(0)); // Disable bypass in Hal_HDMI_init()
5927 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, 0, BIT(5)); // [5]: 0: WR_Clock_Freq in Hal_HDMI_AVG_ScaleringDown()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c3350 W2BYTEMSK(REG_HDMI2_DUAL_0_20_L, btrue, BIT(0)); in Hal_HDMI_Set_YUV422to444_Bypass()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h6031 #define REG_HDMI2_DUAL_0_20_L (REG_HDMI2_DUAL_0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h6033 #define REG_HDMI2_DUAL_0_20_L (REG_HDMI2_DUAL_0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h6023 #define REG_HDMI2_DUAL_0_20_L (REG_HDMI2_DUAL_0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h6033 #define REG_HDMI2_DUAL_0_20_L (REG_HDMI2_DUAL_0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h6023 #define REG_HDMI2_DUAL_0_20_L (REG_HDMI2_DUAL_0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h6033 #define REG_HDMI2_DUAL_0_20_L (REG_HDMI2_DUAL_0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h6033 #define REG_HDMI2_DUAL_0_20_L (REG_HDMI2_DUAL_0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h6023 #define REG_HDMI2_DUAL_0_20_L (REG_HDMI2_DUAL_0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h6024 #define REG_HDMI2_DUAL_0_20_L (REG_HDMI2_DUAL_0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h6023 #define REG_HDMI2_DUAL_0_20_L (REG_HDMI2_DUAL_0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h6031 #define REG_HDMI2_DUAL_0_20_L (REG_HDMI2_DUAL_0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h6031 #define REG_HDMI2_DUAL_0_20_L (REG_HDMI2_DUAL_0_BASE + 0x40) macro

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