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Searched refs:REG_HDMI2_12_L (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_hdmi.c994 W2BYTEMSK(REG_HDMI2_12_L, BIT(0), BIT(0)); in Hal_MHL_TMDS_pkt_reset()
995 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(0)); in Hal_MHL_TMDS_pkt_reset()
998 W2BYTEMSK(REG_HDMI2_12_L, BIT(8), BIT(8)); in Hal_MHL_TMDS_pkt_reset()
999 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(8)); in Hal_MHL_TMDS_pkt_reset()
1037 W2BYTEMSK(REG_HDMI2_12_L, BIT(0), BIT(0)); in Hal_HDMI_pkt_reset()
1038 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(0)); in Hal_HDMI_pkt_reset()
1041 W2BYTEMSK(REG_HDMI2_12_L, BIT(8), BIT(8)); in Hal_HDMI_pkt_reset()
1042 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(8)); in Hal_HDMI_pkt_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_hdmi.c994 W2BYTEMSK(REG_HDMI2_12_L, BIT(0), BIT(0)); in Hal_MHL_TMDS_pkt_reset()
995 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(0)); in Hal_MHL_TMDS_pkt_reset()
998 W2BYTEMSK(REG_HDMI2_12_L, BIT(8), BIT(8)); in Hal_MHL_TMDS_pkt_reset()
999 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(8)); in Hal_MHL_TMDS_pkt_reset()
1037 W2BYTEMSK(REG_HDMI2_12_L, BIT(0), BIT(0)); in Hal_HDMI_pkt_reset()
1038 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(0)); in Hal_HDMI_pkt_reset()
1041 W2BYTEMSK(REG_HDMI2_12_L, BIT(8), BIT(8)); in Hal_HDMI_pkt_reset()
1042 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(8)); in Hal_HDMI_pkt_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c3900 W2BYTEMSK(REG_HDMI2_12_L, BIT(0), BIT(0)); in Hal_MHL_TMDS_pkt_reset()
3901 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(0)); in Hal_MHL_TMDS_pkt_reset()
3904 W2BYTEMSK(REG_HDMI2_12_L, BIT(8), BIT(8)); in Hal_MHL_TMDS_pkt_reset()
3905 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(8)); in Hal_MHL_TMDS_pkt_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c4005 W2BYTEMSK(REG_HDMI2_12_L, BIT(0), BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4006 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4009 W2BYTEMSK(REG_HDMI2_12_L, BIT(8), BIT(8)); in Hal_MHL_TMDS_pkt_reset()
4010 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(8)); in Hal_MHL_TMDS_pkt_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c4005 W2BYTEMSK(REG_HDMI2_12_L, BIT(0), BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4006 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4009 W2BYTEMSK(REG_HDMI2_12_L, BIT(8), BIT(8)); in Hal_MHL_TMDS_pkt_reset()
4010 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(8)); in Hal_MHL_TMDS_pkt_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c4005 W2BYTEMSK(REG_HDMI2_12_L, BIT(0), BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4006 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4009 W2BYTEMSK(REG_HDMI2_12_L, BIT(8), BIT(8)); in Hal_MHL_TMDS_pkt_reset()
4010 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(8)); in Hal_MHL_TMDS_pkt_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c3945 W2BYTEMSK(REG_HDMI2_12_L, BIT(0), BIT(0)); in Hal_MHL_TMDS_pkt_reset()
3946 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(0)); in Hal_MHL_TMDS_pkt_reset()
3949 W2BYTEMSK(REG_HDMI2_12_L, BIT(8), BIT(8)); in Hal_MHL_TMDS_pkt_reset()
3950 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(8)); in Hal_MHL_TMDS_pkt_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c4005 W2BYTEMSK(REG_HDMI2_12_L, BIT(0), BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4006 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4009 W2BYTEMSK(REG_HDMI2_12_L, BIT(8), BIT(8)); in Hal_MHL_TMDS_pkt_reset()
4010 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(8)); in Hal_MHL_TMDS_pkt_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c4576 W2BYTEMSK(REG_HDMI2_12_L, BIT(0), BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4577 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4580 W2BYTEMSK(REG_HDMI2_12_L, BIT(8), BIT(8)); in Hal_MHL_TMDS_pkt_reset()
4581 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(8)); in Hal_MHL_TMDS_pkt_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c4579 W2BYTEMSK(REG_HDMI2_12_L, BIT(0), BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4580 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4583 W2BYTEMSK(REG_HDMI2_12_L, BIT(8), BIT(8)); in Hal_MHL_TMDS_pkt_reset()
4584 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(8)); in Hal_MHL_TMDS_pkt_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c4134 W2BYTEMSK(REG_HDMI2_12_L, BIT(0), BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4135 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4138 W2BYTEMSK(REG_HDMI2_12_L, BIT(8), BIT(8)); in Hal_MHL_TMDS_pkt_reset()
4139 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(8)); in Hal_MHL_TMDS_pkt_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c4582 W2BYTEMSK(REG_HDMI2_12_L, BIT(0), BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4583 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4586 W2BYTEMSK(REG_HDMI2_12_L, BIT(8), BIT(8)); in Hal_MHL_TMDS_pkt_reset()
4587 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(8)); in Hal_MHL_TMDS_pkt_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c4134 W2BYTEMSK(REG_HDMI2_12_L, BIT(0), BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4135 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(0)); in Hal_MHL_TMDS_pkt_reset()
4138 W2BYTEMSK(REG_HDMI2_12_L, BIT(8), BIT(8)); in Hal_MHL_TMDS_pkt_reset()
4139 W2BYTEMSK(REG_HDMI2_12_L, 0, BIT(8)); in Hal_MHL_TMDS_pkt_reset()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h1228 #define REG_HDMI2_12_L (REG_HDMI2_BASE + 0x24) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h1228 #define REG_HDMI2_12_L (REG_HDMI2_BASE + 0x24) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h1210 #define REG_HDMI2_12_L (REG_HDMI2_BASE + 0x24) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h1210 #define REG_HDMI2_12_L (REG_HDMI2_BASE + 0x24) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h1210 #define REG_HDMI2_12_L (REG_HDMI2_BASE + 0x24) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h1210 #define REG_HDMI2_12_L (REG_HDMI2_BASE + 0x24) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h1210 #define REG_HDMI2_12_L (REG_HDMI2_BASE + 0x24) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h1210 #define REG_HDMI2_12_L (REG_HDMI2_BASE + 0x24) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h1210 #define REG_HDMI2_12_L (REG_HDMI2_BASE + 0x24) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h1210 #define REG_HDMI2_12_L (REG_HDMI2_BASE + 0x24) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h1210 #define REG_HDMI2_12_L (REG_HDMI2_BASE + 0x24) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h1210 #define REG_HDMI2_12_L (REG_HDMI2_BASE + 0x24) macro

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