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Searched refs:REG_HDCP_DUAL_P3_02_L (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c2045 … W2BYTEMSK(REG_HDCP_DUAL_P3_02_L, (bEnableFlag?(TMDS_HDCP_WINDOW_END_VALUE << 8): 0), BMASK(15:8)); in _Hal_tmds_SetHDCPWindowEnd()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c2075 … W2BYTEMSK(REG_HDCP_DUAL_P3_02_L, (bEnableFlag?(TMDS_HDCP_WINDOW_END_VALUE << 8): 0), BMASK(15:8)); in _Hal_tmds_SetHDCPWindowEnd()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c2114 … W2BYTEMSK(REG_HDCP_DUAL_P3_02_L, (bEnableFlag?(TMDS_HDCP_WINDOW_END_VALUE << 8): 0), BMASK(15:8)); in _Hal_tmds_SetHDCPWindowEnd()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c2075 … W2BYTEMSK(REG_HDCP_DUAL_P3_02_L, (bEnableFlag?(TMDS_HDCP_WINDOW_END_VALUE << 8): 0), BMASK(15:8)); in _Hal_tmds_SetHDCPWindowEnd()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c2121 … W2BYTEMSK(REG_HDCP_DUAL_P3_02_L, (bEnableFlag?(TMDS_HDCP_WINDOW_END_VALUE << 8): 0), BMASK(15:8)); in _Hal_tmds_SetHDCPWindowEnd()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c2114 … W2BYTEMSK(REG_HDCP_DUAL_P3_02_L, (bEnableFlag?(TMDS_HDCP_WINDOW_END_VALUE << 8): 0), BMASK(15:8)); in _Hal_tmds_SetHDCPWindowEnd()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c2056 … W2BYTEMSK(REG_HDCP_DUAL_P3_02_L, (bEnableFlag?(TMDS_HDCP_WINDOW_END_VALUE << 8): 0), BMASK(15:8)); in _Hal_tmds_SetHDCPWindowEnd()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c2056 … W2BYTEMSK(REG_HDCP_DUAL_P3_02_L, (bEnableFlag?(TMDS_HDCP_WINDOW_END_VALUE << 8): 0), BMASK(15:8)); in _Hal_tmds_SetHDCPWindowEnd()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c2214 … W2BYTEMSK(REG_HDCP_DUAL_P3_02_L, (bEnableFlag?(TMDS_HDCP_WINDOW_END_VALUE << 8): 0), BMASK(15:8)); in _Hal_tmds_SetHDCPWindowEnd()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c2056 … W2BYTEMSK(REG_HDCP_DUAL_P3_02_L, (bEnableFlag?(TMDS_HDCP_WINDOW_END_VALUE << 8): 0), BMASK(15:8)); in _Hal_tmds_SetHDCPWindowEnd()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c2214 … W2BYTEMSK(REG_HDCP_DUAL_P3_02_L, (bEnableFlag?(TMDS_HDCP_WINDOW_END_VALUE << 8): 0), BMASK(15:8)); in _Hal_tmds_SetHDCPWindowEnd()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h5499 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h5501 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h5493 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h5501 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h5493 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h5501 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h5501 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h5493 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h5494 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h5493 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h5499 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h5499 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h5499 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04) macro