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Searched refs:REG_HDCP_DUAL_P1_66_L (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c1981 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P1_66_L); in _Hal_tmds_GetHDCP22IntStatus()
1985 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c2011 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P1_66_L); in _Hal_tmds_GetHDCP22IntStatus()
2015 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c2050 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P1_66_L); in _Hal_tmds_GetHDCP22IntStatus()
2054 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c2011 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P1_66_L); in _Hal_tmds_GetHDCP22IntStatus()
2015 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c2057 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P1_66_L); in _Hal_tmds_GetHDCP22IntStatus()
2061 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c2050 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P1_66_L); in _Hal_tmds_GetHDCP22IntStatus()
2054 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c1992 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P1_66_L); in _Hal_tmds_GetHDCP22IntStatus()
1996 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c1992 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P1_66_L); in _Hal_tmds_GetHDCP22IntStatus()
1996 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c2150 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P1_66_L); in _Hal_tmds_GetHDCP22IntStatus()
2154 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c1992 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P1_66_L); in _Hal_tmds_GetHDCP22IntStatus()
1996 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c2150 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P1_66_L); in _Hal_tmds_GetHDCP22IntStatus()
2154 W2BYTE(REG_HDCP_DUAL_P1_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h4627 #define REG_HDCP_DUAL_P1_66_L (REG_HDCP_DUAL_P1_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h4629 #define REG_HDCP_DUAL_P1_66_L (REG_HDCP_DUAL_P1_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h4625 #define REG_HDCP_DUAL_P1_66_L (REG_HDCP_DUAL_P1_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h4629 #define REG_HDCP_DUAL_P1_66_L (REG_HDCP_DUAL_P1_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h4625 #define REG_HDCP_DUAL_P1_66_L (REG_HDCP_DUAL_P1_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h4629 #define REG_HDCP_DUAL_P1_66_L (REG_HDCP_DUAL_P1_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h4629 #define REG_HDCP_DUAL_P1_66_L (REG_HDCP_DUAL_P1_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h4625 #define REG_HDCP_DUAL_P1_66_L (REG_HDCP_DUAL_P1_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h4626 #define REG_HDCP_DUAL_P1_66_L (REG_HDCP_DUAL_P1_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h4625 #define REG_HDCP_DUAL_P1_66_L (REG_HDCP_DUAL_P1_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h4627 #define REG_HDCP_DUAL_P1_66_L (REG_HDCP_DUAL_P1_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h4627 #define REG_HDCP_DUAL_P1_66_L (REG_HDCP_DUAL_P1_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h4627 #define REG_HDCP_DUAL_P1_66_L (REG_HDCP_DUAL_P1_BASE + 0xCC) macro