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Searched refs:REG_HDCP_DUAL_P0_66_L (Results 1 – 25 of 26) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c1004 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P0_66_L); in _Hal_tmds_GetHDCP22IntStatus()
1008 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
2100 W2BYTEMSK(REG_HDCP_DUAL_P0_66_L, 0x3F, 0x3F); in Hal_HDCP22_PortInit()
2101 W2BYTEMSK(REG_HDCP_DUAL_P0_66_L, 0x00, 0x3F); in Hal_HDCP22_PortInit()
2112 if(R2BYTE(REG_HDCP_DUAL_P0_66_L) & BIT(2)) //check write done in Hal_HDCP22_PollingWriteDone()
2115 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
2133 if(R2BYTE(REG_HDCP_DUAL_P0_66_L) & BIT(3)) //check read done in Hal_HDCP22_PollingReadDone()
2136 W2BYTEMSK(REG_HDCP_DUAL_P0_66_L, BIT(3), BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c1397 W2BYTEMSK(REG_HDCP_DUAL_P0_66_L, 0x3F, 0x3F); in Hal_HDCP22_PortInit()
1398 W2BYTEMSK(REG_HDCP_DUAL_P0_66_L, 0x00, 0x3F); in Hal_HDCP22_PortInit()
1409 if(R2BYTE(REG_HDCP_DUAL_P0_66_L) & BIT(2)) //check write done in Hal_HDCP22_PollingWriteDone()
1412 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
1430 if(R2BYTE(REG_HDCP_DUAL_P0_66_L) & BIT(3)) //check read done in Hal_HDCP22_PollingReadDone()
1433 W2BYTEMSK(REG_HDCP_DUAL_P0_66_L, BIT(3), BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c1971 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P0_66_L); in _Hal_tmds_GetHDCP22IntStatus()
1975 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3311 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3312 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
3326 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(2)) //check write done in Hal_HDCP22_PollingWriteDone()
3329 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
3350 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(3)) //check read done in Hal_HDCP22_PollingReadDone()
3353 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c2001 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P0_66_L); in _Hal_tmds_GetHDCP22IntStatus()
2005 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3430 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3431 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
3448 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(2)) //check write done in Hal_HDCP22_PollingWriteDone()
3451 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
3472 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(3)) //check read done in Hal_HDCP22_PollingReadDone()
3475 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c2040 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P0_66_L); in _Hal_tmds_GetHDCP22IntStatus()
2044 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3341 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3342 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
3363 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(2)) //check write done in Hal_HDCP22_PollingWriteDone()
3366 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
3391 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(3)) //check read done in Hal_HDCP22_PollingReadDone()
3394 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c2001 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P0_66_L); in _Hal_tmds_GetHDCP22IntStatus()
2005 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3430 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3431 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
3448 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(2)) //check write done in Hal_HDCP22_PollingWriteDone()
3451 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
3472 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(3)) //check read done in Hal_HDCP22_PollingReadDone()
3475 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c2047 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P0_66_L); in _Hal_tmds_GetHDCP22IntStatus()
2051 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3325 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3326 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
3343 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(2)) //check write done in Hal_HDCP22_PollingWriteDone()
3346 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
3367 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(3)) //check read done in Hal_HDCP22_PollingReadDone()
3370 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c2040 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P0_66_L); in _Hal_tmds_GetHDCP22IntStatus()
2044 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3341 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3342 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
3363 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(2)) //check write done in Hal_HDCP22_PollingWriteDone()
3366 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
3391 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(3)) //check read done in Hal_HDCP22_PollingReadDone()
3394 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c1982 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P0_66_L); in _Hal_tmds_GetHDCP22IntStatus()
1986 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3981 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3982 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
3996 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(2)) //check write done in Hal_HDCP22_PollingWriteDone()
3999 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
4020 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(3)) //check read done in Hal_HDCP22_PollingReadDone()
4023 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c1982 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P0_66_L); in _Hal_tmds_GetHDCP22IntStatus()
1986 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3984 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3985 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
3999 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(2)) //check write done in Hal_HDCP22_PollingWriteDone()
4002 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
4023 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(3)) //check read done in Hal_HDCP22_PollingReadDone()
4026 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c2140 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P0_66_L); in _Hal_tmds_GetHDCP22IntStatus()
2144 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3514 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3515 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
3532 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(2)) //check write done in Hal_HDCP22_PollingWriteDone()
3535 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
3556 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(3)) //check read done in Hal_HDCP22_PollingReadDone()
3559 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c1982 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P0_66_L); in _Hal_tmds_GetHDCP22IntStatus()
1986 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3984 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3985 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
4002 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(2)) //check write done in Hal_HDCP22_PollingWriteDone()
4005 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
4026 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(3)) //check read done in Hal_HDCP22_PollingReadDone()
4029 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c2140 ulHDCP22Status = R2BYTE(REG_HDCP_DUAL_P0_66_L); in _Hal_tmds_GetHDCP22IntStatus()
2144 W2BYTE(REG_HDCP_DUAL_P0_66_L, BIT(1)); in _Hal_tmds_GetHDCP22IntStatus()
3514 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x3D); in Hal_HDCP22_PortInit()
3515 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, 0x00); in Hal_HDCP22_PortInit()
3532 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(2)) //check write done in Hal_HDCP22_PollingWriteDone()
3535 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(4)| BIT(2)); //clear write done, write start in Hal_HDCP22_PollingWriteDone()
3556 if(R2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset) & BIT(3)) //check read done in Hal_HDCP22_PollingReadDone()
3559 W2BYTE(REG_HDCP_DUAL_P0_66_L + dwBKOffset, BIT(3)); //clear read done in Hal_HDCP22_PollingReadDone()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h4091 #define REG_HDCP_DUAL_P0_66_L (REG_HDCP_DUAL_P0_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h4093 #define REG_HDCP_DUAL_P0_66_L (REG_HDCP_DUAL_P0_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h4091 #define REG_HDCP_DUAL_P0_66_L (REG_HDCP_DUAL_P0_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h4093 #define REG_HDCP_DUAL_P0_66_L (REG_HDCP_DUAL_P0_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h4091 #define REG_HDCP_DUAL_P0_66_L (REG_HDCP_DUAL_P0_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h4093 #define REG_HDCP_DUAL_P0_66_L (REG_HDCP_DUAL_P0_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h4093 #define REG_HDCP_DUAL_P0_66_L (REG_HDCP_DUAL_P0_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h4091 #define REG_HDCP_DUAL_P0_66_L (REG_HDCP_DUAL_P0_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h4092 #define REG_HDCP_DUAL_P0_66_L (REG_HDCP_DUAL_P0_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h4091 #define REG_HDCP_DUAL_P0_66_L (REG_HDCP_DUAL_P0_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h4091 #define REG_HDCP_DUAL_P0_66_L (REG_HDCP_DUAL_P0_BASE + 0xCC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h4091 #define REG_HDCP_DUAL_P0_66_L (REG_HDCP_DUAL_P0_BASE + 0xCC) macro

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