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Searched refs:REG_HDCP_DUAL_P0_65_L (Results 1 – 25 of 25) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c3275 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(10), BIT(10)); //re-auth overwrite enable in _Hal_HDCP22_SetReAuthBit()
3276 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(11), BIT(11)); in _Hal_HDCP22_SetReAuthBit()
3277 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, 0x00, BIT(10)); //clear overwrite in _Hal_HDCP22_SetReAuthBit()
3281 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(12), BIT(12)); //clear in _Hal_HDCP22_SetReAuthBit()
6150 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(15) | BIT(14), BIT(15) | BIT(14)); in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c3302 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(10), BIT(10)); //re-auth overwrite enable in _Hal_HDCP22_SetReAuthBit()
3303 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(11), BIT(11)); in _Hal_HDCP22_SetReAuthBit()
3304 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, 0x00, BIT(10)); //clear overwrite in _Hal_HDCP22_SetReAuthBit()
3308 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(12), BIT(12)); //clear in _Hal_HDCP22_SetReAuthBit()
6204 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(15) | BIT(14), BIT(15) | BIT(14)); in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c3305 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(10), BIT(10)); //re-auth overwrite enable in _Hal_HDCP22_SetReAuthBit()
3306 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(11), BIT(11)); in _Hal_HDCP22_SetReAuthBit()
3307 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, 0x00, BIT(10)); //clear overwrite in _Hal_HDCP22_SetReAuthBit()
3311 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(12), BIT(12)); //clear in _Hal_HDCP22_SetReAuthBit()
6273 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(15) | BIT(14), BIT(15) | BIT(14)); in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c3302 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(10), BIT(10)); //re-auth overwrite enable in _Hal_HDCP22_SetReAuthBit()
3303 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(11), BIT(11)); in _Hal_HDCP22_SetReAuthBit()
3304 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, 0x00, BIT(10)); //clear overwrite in _Hal_HDCP22_SetReAuthBit()
3308 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(12), BIT(12)); //clear in _Hal_HDCP22_SetReAuthBit()
6204 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(15) | BIT(14), BIT(15) | BIT(14)); in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c3305 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(10), BIT(10)); //re-auth overwrite enable in _Hal_HDCP22_SetReAuthBit()
3306 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(11), BIT(11)); in _Hal_HDCP22_SetReAuthBit()
3307 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, 0x00, BIT(10)); //clear overwrite in _Hal_HDCP22_SetReAuthBit()
3311 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(12), BIT(12)); //clear in _Hal_HDCP22_SetReAuthBit()
6273 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(15) | BIT(14), BIT(15) | BIT(14)); in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c3293 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(10), BIT(10)); //re-auth overwrite enable in _Hal_HDCP22_SetReAuthBit()
3294 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(11), BIT(11)); in _Hal_HDCP22_SetReAuthBit()
3295 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, 0x00, BIT(10)); //clear overwrite in _Hal_HDCP22_SetReAuthBit()
3299 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(12), BIT(12)); //clear in _Hal_HDCP22_SetReAuthBit()
6867 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(15) | BIT(14), BIT(15) | BIT(14)); in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c3296 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(10), BIT(10)); //re-auth overwrite enable in _Hal_HDCP22_SetReAuthBit()
3297 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(11), BIT(11)); in _Hal_HDCP22_SetReAuthBit()
3298 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, 0x00, BIT(10)); //clear overwrite in _Hal_HDCP22_SetReAuthBit()
3302 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(12), BIT(12)); //clear in _Hal_HDCP22_SetReAuthBit()
6870 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(15) | BIT(14), BIT(15) | BIT(14)); in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c3478 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(10), BIT(10)); //re-auth overwrite enable in _Hal_HDCP22_SetReAuthBit()
3479 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(11), BIT(11)); in _Hal_HDCP22_SetReAuthBit()
3480 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, 0x00, BIT(10)); //clear overwrite in _Hal_HDCP22_SetReAuthBit()
3484 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(12), BIT(12)); //clear in _Hal_HDCP22_SetReAuthBit()
6641 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(15) | BIT(14), BIT(15) | BIT(14)); in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c3296 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(10), BIT(10)); //re-auth overwrite enable in _Hal_HDCP22_SetReAuthBit()
3297 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(11), BIT(11)); in _Hal_HDCP22_SetReAuthBit()
3298 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, 0x00, BIT(10)); //clear overwrite in _Hal_HDCP22_SetReAuthBit()
3302 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(12), BIT(12)); //clear in _Hal_HDCP22_SetReAuthBit()
6873 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(15) | BIT(14), BIT(15) | BIT(14)); in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c3478 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(10), BIT(10)); //re-auth overwrite enable in _Hal_HDCP22_SetReAuthBit()
3479 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(11), BIT(11)); in _Hal_HDCP22_SetReAuthBit()
3480 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, 0x00, BIT(10)); //clear overwrite in _Hal_HDCP22_SetReAuthBit()
3484 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(12), BIT(12)); //clear in _Hal_HDCP22_SetReAuthBit()
6641 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(15) | BIT(14), BIT(15) | BIT(14)); in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c4490 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L, BIT(15) | BIT(14), BIT(15) | BIT(14)); in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c6271 W2BYTEMSK(REG_HDCP_DUAL_P0_65_L + dwBKOffset, BIT(15) | BIT(14), BIT(15) | BIT(14)); in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h4089 #define REG_HDCP_DUAL_P0_65_L (REG_HDCP_DUAL_P0_BASE + 0xCA) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h4091 #define REG_HDCP_DUAL_P0_65_L (REG_HDCP_DUAL_P0_BASE + 0xCA) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h4089 #define REG_HDCP_DUAL_P0_65_L (REG_HDCP_DUAL_P0_BASE + 0xCA) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h4091 #define REG_HDCP_DUAL_P0_65_L (REG_HDCP_DUAL_P0_BASE + 0xCA) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h4089 #define REG_HDCP_DUAL_P0_65_L (REG_HDCP_DUAL_P0_BASE + 0xCA) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h4091 #define REG_HDCP_DUAL_P0_65_L (REG_HDCP_DUAL_P0_BASE + 0xCA) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h4091 #define REG_HDCP_DUAL_P0_65_L (REG_HDCP_DUAL_P0_BASE + 0xCA) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h4089 #define REG_HDCP_DUAL_P0_65_L (REG_HDCP_DUAL_P0_BASE + 0xCA) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h4090 #define REG_HDCP_DUAL_P0_65_L (REG_HDCP_DUAL_P0_BASE + 0xCA) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h4089 #define REG_HDCP_DUAL_P0_65_L (REG_HDCP_DUAL_P0_BASE + 0xCA) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h4089 #define REG_HDCP_DUAL_P0_65_L (REG_HDCP_DUAL_P0_BASE + 0xCA) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h4089 #define REG_HDCP_DUAL_P0_65_L (REG_HDCP_DUAL_P0_BASE + 0xCA) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h4089 #define REG_HDCP_DUAL_P0_65_L (REG_HDCP_DUAL_P0_BASE + 0xCA) macro