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Searched refs:REG_HDCP_DUAL_P0_64_L (Results 1 – 25 of 26) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c2094 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L, BIT(15), BIT(15)); in Hal_HDCP22_PortInit()
2252 dwMsgLen = R2BYTE(REG_HDCP_DUAL_P0_64_L) & BMASK(9:0); in Hal_HDCP22_RecvMsg()
2314 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L, BIT(15), BIT(15)); // address pulse in Hal_HDCP22_SendMsg()
4489 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L, BIT(15), BIT(15)); // address pulse in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c1391 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L, BIT(15), BIT(15)); in Hal_HDCP22_PortInit()
1549 dwMsgLen = R2BYTE(REG_HDCP_DUAL_P0_64_L) & BMASK(9:0); in Hal_HDCP22_RecvMsg()
1611 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L, BIT(15), BIT(15)); // address pulse in Hal_HDCP22_SendMsg()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c3305 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); in Hal_HDCP22_PortInit()
3479 dwMsgLen = R2BYTE(REG_HDCP_DUAL_P0_64_L + dwBKOffset) & BMASK(9:0); in Hal_HDCP22_RecvMsg()
3569 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP22_SendMsg()
6149 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c3424 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); in Hal_HDCP22_PortInit()
3603 dwMsgLen = R2BYTE(REG_HDCP_DUAL_P0_64_L + dwBKOffset) & BMASK(9:0); in Hal_HDCP22_RecvMsg()
3693 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP22_SendMsg()
6203 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c3335 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); in Hal_HDCP22_PortInit()
3535 dwMsgLen = R2BYTE(REG_HDCP_DUAL_P0_64_L + dwBKOffset) & BMASK(9:0); in Hal_HDCP22_RecvMsg()
3630 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP22_SendMsg()
6272 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c3424 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); in Hal_HDCP22_PortInit()
3603 dwMsgLen = R2BYTE(REG_HDCP_DUAL_P0_64_L + dwBKOffset) & BMASK(9:0); in Hal_HDCP22_RecvMsg()
3693 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP22_SendMsg()
6203 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c3319 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); in Hal_HDCP22_PortInit()
3496 dwMsgLen = R2BYTE(REG_HDCP_DUAL_P0_64_L + dwBKOffset) & BMASK(9:0); in Hal_HDCP22_RecvMsg()
3586 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP22_SendMsg()
6270 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c3335 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); in Hal_HDCP22_PortInit()
3535 dwMsgLen = R2BYTE(REG_HDCP_DUAL_P0_64_L + dwBKOffset) & BMASK(9:0); in Hal_HDCP22_RecvMsg()
3630 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP22_SendMsg()
6272 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c3975 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); in Hal_HDCP22_PortInit()
4149 dwMsgLen = R2BYTE(REG_HDCP_DUAL_P0_64_L + dwBKOffset) & BMASK(9:0); in Hal_HDCP22_RecvMsg()
4239 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP22_SendMsg()
6866 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c3978 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); in Hal_HDCP22_PortInit()
4152 dwMsgLen = R2BYTE(REG_HDCP_DUAL_P0_64_L + dwBKOffset) & BMASK(9:0); in Hal_HDCP22_RecvMsg()
4242 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP22_SendMsg()
6869 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c3508 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); in Hal_HDCP22_PortInit()
3685 dwMsgLen = R2BYTE(REG_HDCP_DUAL_P0_64_L + dwBKOffset) & BMASK(9:0); in Hal_HDCP22_RecvMsg()
3775 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP22_SendMsg()
6640 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c3978 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); in Hal_HDCP22_PortInit()
4155 dwMsgLen = R2BYTE(REG_HDCP_DUAL_P0_64_L + dwBKOffset) & BMASK(9:0); in Hal_HDCP22_RecvMsg()
4245 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP22_SendMsg()
6872 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c3508 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); in Hal_HDCP22_PortInit()
3685 dwMsgLen = R2BYTE(REG_HDCP_DUAL_P0_64_L + dwBKOffset) & BMASK(9:0); in Hal_HDCP22_RecvMsg()
3775 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP22_SendMsg()
6640 W2BYTEMSK(REG_HDCP_DUAL_P0_64_L + dwBKOffset, BIT(15), BIT(15)); // address pulse in Hal_HDCP_WriteKSVList()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h4087 #define REG_HDCP_DUAL_P0_64_L (REG_HDCP_DUAL_P0_BASE + 0xC8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h4089 #define REG_HDCP_DUAL_P0_64_L (REG_HDCP_DUAL_P0_BASE + 0xC8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h4087 #define REG_HDCP_DUAL_P0_64_L (REG_HDCP_DUAL_P0_BASE + 0xC8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h4089 #define REG_HDCP_DUAL_P0_64_L (REG_HDCP_DUAL_P0_BASE + 0xC8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h4087 #define REG_HDCP_DUAL_P0_64_L (REG_HDCP_DUAL_P0_BASE + 0xC8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h4089 #define REG_HDCP_DUAL_P0_64_L (REG_HDCP_DUAL_P0_BASE + 0xC8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h4089 #define REG_HDCP_DUAL_P0_64_L (REG_HDCP_DUAL_P0_BASE + 0xC8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h4087 #define REG_HDCP_DUAL_P0_64_L (REG_HDCP_DUAL_P0_BASE + 0xC8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h4088 #define REG_HDCP_DUAL_P0_64_L (REG_HDCP_DUAL_P0_BASE + 0xC8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h4087 #define REG_HDCP_DUAL_P0_64_L (REG_HDCP_DUAL_P0_BASE + 0xC8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h4087 #define REG_HDCP_DUAL_P0_64_L (REG_HDCP_DUAL_P0_BASE + 0xC8) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h4087 #define REG_HDCP_DUAL_P0_64_L (REG_HDCP_DUAL_P0_BASE + 0xC8) macro

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