| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 2093 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L, 0x00, BMASK(9:0)); in Hal_HDCP22_PortInit()
2304 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L, dwDataLen, 0x7FF); // write length in Hal_HDCP22_SendMsg()
4487 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L, ulDataLen, 0x7FF); // write length in Hal_HDCP_WriteKSVList()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 1390 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L, 0x00, BMASK(9:0)); in Hal_HDCP22_PortInit()
1601 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L, dwDataLen, 0x7FF); // write length in Hal_HDCP22_SendMsg()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 3304 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, 0x00, BMASK(9:0)); in Hal_HDCP22_PortInit()
3559 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, dwDataLen, 0x7FF); // write length in Hal_HDCP22_SendMsg()
6147 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, ulDataLen, 0x7FF); // write length in Hal_HDCP_WriteKSVList()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 3423 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, 0x00, BMASK(9:0)); in Hal_HDCP22_PortInit()
3683 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, dwDataLen, 0x7FF); // write length in Hal_HDCP22_SendMsg()
6201 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, ulDataLen, 0x7FF); // write length in Hal_HDCP_WriteKSVList()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 3334 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, 0x00, BMASK(9:0)); in Hal_HDCP22_PortInit()
3620 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, dwDataLen, 0x7FF); // write length in Hal_HDCP22_SendMsg()
6270 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, ulDataLen, 0x7FF); // write length in Hal_HDCP_WriteKSVList()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 3423 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, 0x00, BMASK(9:0)); in Hal_HDCP22_PortInit()
3683 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, dwDataLen, 0x7FF); // write length in Hal_HDCP22_SendMsg()
6201 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, ulDataLen, 0x7FF); // write length in Hal_HDCP_WriteKSVList()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 3318 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, 0x00, BMASK(9:0)); in Hal_HDCP22_PortInit()
3576 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, dwDataLen, 0x7FF); // write length in Hal_HDCP22_SendMsg()
6268 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, ulDataLen, 0x7FF); // write length in Hal_HDCP_WriteKSVList()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 3334 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, 0x00, BMASK(9:0)); in Hal_HDCP22_PortInit()
3620 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, dwDataLen, 0x7FF); // write length in Hal_HDCP22_SendMsg()
6270 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, ulDataLen, 0x7FF); // write length in Hal_HDCP_WriteKSVList()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 3974 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, 0x00, BMASK(9:0)); in Hal_HDCP22_PortInit()
4229 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, dwDataLen, 0x7FF); // write length in Hal_HDCP22_SendMsg()
6864 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, ulDataLen, 0x7FF); // write length in Hal_HDCP_WriteKSVList()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 3977 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, 0x00, BMASK(9:0)); in Hal_HDCP22_PortInit()
4232 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, dwDataLen, 0x7FF); // write length in Hal_HDCP22_SendMsg()
6867 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, ulDataLen, 0x7FF); // write length in Hal_HDCP_WriteKSVList()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 3507 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, 0x00, BMASK(9:0)); in Hal_HDCP22_PortInit()
3765 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, dwDataLen, 0x7FF); // write length in Hal_HDCP22_SendMsg()
6638 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, ulDataLen, 0x7FF); // write length in Hal_HDCP_WriteKSVList()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 3977 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, 0x00, BMASK(9:0)); in Hal_HDCP22_PortInit()
4235 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, dwDataLen, 0x7FF); // write length in Hal_HDCP22_SendMsg()
6870 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, ulDataLen, 0x7FF); // write length in Hal_HDCP_WriteKSVList()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 3507 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, 0x00, BMASK(9:0)); in Hal_HDCP22_PortInit()
3765 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, dwDataLen, 0x7FF); // write length in Hal_HDCP22_SendMsg()
6638 W2BYTEMSK(REG_HDCP_DUAL_P0_63_L + dwBKOffset, ulDataLen, 0x7FF); // write length in Hal_HDCP_WriteKSVList()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 4085 #define REG_HDCP_DUAL_P0_63_L (REG_HDCP_DUAL_P0_BASE + 0xC6) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 4087 #define REG_HDCP_DUAL_P0_63_L (REG_HDCP_DUAL_P0_BASE + 0xC6) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 4085 #define REG_HDCP_DUAL_P0_63_L (REG_HDCP_DUAL_P0_BASE + 0xC6) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 4087 #define REG_HDCP_DUAL_P0_63_L (REG_HDCP_DUAL_P0_BASE + 0xC6) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 4085 #define REG_HDCP_DUAL_P0_63_L (REG_HDCP_DUAL_P0_BASE + 0xC6) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 4087 #define REG_HDCP_DUAL_P0_63_L (REG_HDCP_DUAL_P0_BASE + 0xC6) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 4087 #define REG_HDCP_DUAL_P0_63_L (REG_HDCP_DUAL_P0_BASE + 0xC6) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 4085 #define REG_HDCP_DUAL_P0_63_L (REG_HDCP_DUAL_P0_BASE + 0xC6) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 4086 #define REG_HDCP_DUAL_P0_63_L (REG_HDCP_DUAL_P0_BASE + 0xC6) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 4085 #define REG_HDCP_DUAL_P0_63_L (REG_HDCP_DUAL_P0_BASE + 0xC6) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 4085 #define REG_HDCP_DUAL_P0_63_L (REG_HDCP_DUAL_P0_BASE + 0xC6) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 4085 #define REG_HDCP_DUAL_P0_63_L (REG_HDCP_DUAL_P0_BASE + 0xC6) macro
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