| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 2002 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
2005 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
2010 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(4), BIT(4)); // trigger latch data in _Hal_tmds_HDCPWriteX74()
2013 while(R2BYTE(REG_HDCP_DUAL_P0_19_L +u16bank_offset) & BIT(7)); // wait write ready in _Hal_tmds_HDCPWriteX74()
2016 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, 0, BIT(15)|BIT(14)); // [15]: CPU write disa… in _Hal_tmds_HDCPWriteX74()
2084 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
2087 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
2090 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(4), BIT(4)); //HDCP data write port pulse generate in Hal_HDCP22_PortInit()
2311 while((R2BYTE(REG_HDCP_DUAL_P0_19_L) & BIT(10))); //polling DDC free in Hal_HDCP22_SendMsg()
2490 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write enable, [14]: … in Hal_HDCP_initproductionkey()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 3332 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
3335 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
3340 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(4), BIT(4)); // trigger latch data in _Hal_tmds_HDCPWriteX74()
3343 while(R2BYTE(REG_HDCP_DUAL_P0_19_L +u16bank_offset) & BIT(7)); // wait write ready in _Hal_tmds_HDCPWriteX74()
3346 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, 0, BIT(15)|BIT(14)); // [15]: CPU write disa… in _Hal_tmds_HDCPWriteX74()
3414 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
3417 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
3420 …W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(4), BIT(4)); //HDCP data write port pulse genera… in Hal_HDCP22_PortInit()
3690 while((R2BYTE(REG_HDCP_DUAL_P0_19_L + dwBKOffset) & BIT(10))); //polling DDC free in Hal_HDCP22_SendMsg()
3893 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 3332 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
3335 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
3340 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(4), BIT(4)); // trigger latch data in _Hal_tmds_HDCPWriteX74()
3343 while(R2BYTE(REG_HDCP_DUAL_P0_19_L +u16bank_offset) & BIT(7)); // wait write ready in _Hal_tmds_HDCPWriteX74()
3346 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, 0, BIT(15)|BIT(14)); // [15]: CPU write disa… in _Hal_tmds_HDCPWriteX74()
3414 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
3417 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
3420 …W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(4), BIT(4)); //HDCP data write port pulse genera… in Hal_HDCP22_PortInit()
3690 while((R2BYTE(REG_HDCP_DUAL_P0_19_L + dwBKOffset) & BIT(10))); //polling DDC free in Hal_HDCP22_SendMsg()
3893 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 3873 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
3876 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
3881 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(4), BIT(4)); // trigger latch data in _Hal_tmds_HDCPWriteX74()
3884 while(R2BYTE(REG_HDCP_DUAL_P0_19_L +u16bank_offset) & BIT(7)); // wait write ready in _Hal_tmds_HDCPWriteX74()
3887 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, 0, BIT(15)|BIT(14)); // [15]: CPU write disa… in _Hal_tmds_HDCPWriteX74()
3965 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
3968 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
3971 …W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(4), BIT(4)); //HDCP data write port pulse genera… in Hal_HDCP22_PortInit()
4236 while((R2BYTE(REG_HDCP_DUAL_P0_19_L + dwBKOffset) & BIT(10))); //polling DDC free in Hal_HDCP22_SendMsg()
4455 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 3876 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
3879 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
3884 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(4), BIT(4)); // trigger latch data in _Hal_tmds_HDCPWriteX74()
3887 while(R2BYTE(REG_HDCP_DUAL_P0_19_L +u16bank_offset) & BIT(7)); // wait write ready in _Hal_tmds_HDCPWriteX74()
3890 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, 0, BIT(15)|BIT(14)); // [15]: CPU write disa… in _Hal_tmds_HDCPWriteX74()
3968 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
3971 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
3974 …W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(4), BIT(4)); //HDCP data write port pulse genera… in Hal_HDCP22_PortInit()
4239 while((R2BYTE(REG_HDCP_DUAL_P0_19_L + dwBKOffset) & BIT(10))); //polling DDC free in Hal_HDCP22_SendMsg()
4458 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 3876 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
3879 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
3884 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(4), BIT(4)); // trigger latch data in _Hal_tmds_HDCPWriteX74()
3887 while(R2BYTE(REG_HDCP_DUAL_P0_19_L +u16bank_offset) & BIT(7)); // wait write ready in _Hal_tmds_HDCPWriteX74()
3890 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, 0, BIT(15)|BIT(14)); // [15]: CPU write disa… in _Hal_tmds_HDCPWriteX74()
3968 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
3971 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
3974 …W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(4), BIT(4)); //HDCP data write port pulse genera… in Hal_HDCP22_PortInit()
4242 while((R2BYTE(REG_HDCP_DUAL_P0_19_L + dwBKOffset) & BIT(10))); //polling DDC free in Hal_HDCP22_SendMsg()
4461 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 3295 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
3298 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
3301 …W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(4), BIT(4)); //HDCP data write port pulse genera… in Hal_HDCP22_PortInit()
3566 while((R2BYTE(REG_HDCP_DUAL_P0_19_L + dwBKOffset) & BIT(10))); //polling DDC free in Hal_HDCP22_SendMsg()
3783 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
3786 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3790 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
3794 while(R2BYTE(REG_HDCP_DUAL_P0_19_L+u16bank_offset) & BIT(7)); // wait write ready in Hal_HDCP_initproductionkey()
3799 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3802 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 3325 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
3328 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
3331 …W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(4), BIT(4)); //HDCP data write port pulse genera… in Hal_HDCP22_PortInit()
3627 while((R2BYTE(REG_HDCP_DUAL_P0_19_L + dwBKOffset) & BIT(10))); //polling DDC free in Hal_HDCP22_SendMsg()
3883 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
3886 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3890 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
3894 while(R2BYTE(REG_HDCP_DUAL_P0_19_L+u16bank_offset) & BIT(7)); // wait write ready in Hal_HDCP_initproductionkey()
3899 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3902 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 3309 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
3312 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
3315 …W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(4), BIT(4)); //HDCP data write port pulse genera… in Hal_HDCP22_PortInit()
3583 while((R2BYTE(REG_HDCP_DUAL_P0_19_L + dwBKOffset) & BIT(10))); //polling DDC free in Hal_HDCP22_SendMsg()
3828 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
3831 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3835 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
3839 while(R2BYTE(REG_HDCP_DUAL_P0_19_L+u16bank_offset) & BIT(7)); // wait write ready in Hal_HDCP_initproductionkey()
3844 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3847 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 3325 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
3328 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
3331 …W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(4), BIT(4)); //HDCP data write port pulse genera… in Hal_HDCP22_PortInit()
3627 while((R2BYTE(REG_HDCP_DUAL_P0_19_L + dwBKOffset) & BIT(10))); //polling DDC free in Hal_HDCP22_SendMsg()
3883 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
3886 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3890 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
3894 while(R2BYTE(REG_HDCP_DUAL_P0_19_L+u16bank_offset) & BIT(7)); // wait write ready in Hal_HDCP_initproductionkey()
3899 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3902 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 3498 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
3501 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
3504 …W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(4), BIT(4)); //HDCP data write port pulse genera… in Hal_HDCP22_PortInit()
3772 while((R2BYTE(REG_HDCP_DUAL_P0_19_L + dwBKOffset) & BIT(10))); //polling DDC free in Hal_HDCP22_SendMsg()
4017 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
4020 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
4024 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
4028 while(R2BYTE(REG_HDCP_DUAL_P0_19_L+u16bank_offset) & BIT(7)); // wait write ready in Hal_HDCP_initproductionkey()
4033 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
4036 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 3498 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
3501 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
3504 …W2BYTEMSK(REG_HDCP_DUAL_P0_19_L + dwBKOffset, BIT(4), BIT(4)); //HDCP data write port pulse genera… in Hal_HDCP22_PortInit()
3772 while((R2BYTE(REG_HDCP_DUAL_P0_19_L + dwBKOffset) & BIT(10))); //polling DDC free in Hal_HDCP22_SendMsg()
4017 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
4020 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
4024 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
4028 while(R2BYTE(REG_HDCP_DUAL_P0_19_L+u16bank_offset) & BIT(7)); // wait write ready in Hal_HDCP_initproductionkey()
4033 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
4036 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 1381 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
1384 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
1387 W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(4), BIT(4)); //HDCP data write port pulse generate in Hal_HDCP22_PortInit()
1608 while((R2BYTE(REG_HDCP_DUAL_P0_19_L) & BIT(10))); //polling DDC free in Hal_HDCP22_SendMsg()
1759 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write enable, [14]: … in Hal_HDCP_initproductionkey()
1762 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
1766 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
1772 while(R2BYTE(REG_HDCP_DUAL_P0_19_L) & BIT(7)); // wait write ready in Hal_HDCP_initproductionkey()
1777 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
1780 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 3937 #define REG_HDCP_DUAL_P0_19_L (REG_HDCP_DUAL_P0_BASE + 0x32) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 3939 #define REG_HDCP_DUAL_P0_19_L (REG_HDCP_DUAL_P0_BASE + 0x32) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 3937 #define REG_HDCP_DUAL_P0_19_L (REG_HDCP_DUAL_P0_BASE + 0x32) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 3939 #define REG_HDCP_DUAL_P0_19_L (REG_HDCP_DUAL_P0_BASE + 0x32) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 3937 #define REG_HDCP_DUAL_P0_19_L (REG_HDCP_DUAL_P0_BASE + 0x32) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 3939 #define REG_HDCP_DUAL_P0_19_L (REG_HDCP_DUAL_P0_BASE + 0x32) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 3939 #define REG_HDCP_DUAL_P0_19_L (REG_HDCP_DUAL_P0_BASE + 0x32) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 3937 #define REG_HDCP_DUAL_P0_19_L (REG_HDCP_DUAL_P0_BASE + 0x32) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 3938 #define REG_HDCP_DUAL_P0_19_L (REG_HDCP_DUAL_P0_BASE + 0x32) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 3937 #define REG_HDCP_DUAL_P0_19_L (REG_HDCP_DUAL_P0_BASE + 0x32) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 3937 #define REG_HDCP_DUAL_P0_19_L (REG_HDCP_DUAL_P0_BASE + 0x32) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 3937 #define REG_HDCP_DUAL_P0_19_L (REG_HDCP_DUAL_P0_BASE + 0x32) macro
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