| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 2001 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
2004 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
2083 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, BIT(10), BIT(10)); //HDCP enalbe for DDC in Hal_HDCP22_PortInit()
2086 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x50, BMASK(9:0)); //CPU r/w address in Hal_HDCP22_PortInit()
2489 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, BIT(10), BIT(10)); // [10]: HDCP enable for DDC in Hal_HDCP_initproductionkey()
2492 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
2507 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
2555 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, (bEnable ? BIT(10):0), BIT(10)); // HDCP enable for ddc in Hal_HDCP_ddc_en()
2757 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, BIT(13), BIT(13)); // [13]: when detect no input, rest HDCP FSM t… in Hal_HDMI_init()
4372 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, BIT(10), BIT(10)); // [10]: HDCP enable for DDC in Hal_HDCP_WriteX74()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 3331 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
3334 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
3413 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, BIT(10), BIT(10)); //HDCP enalbe for DDC in Hal_HDCP22_PortInit()
3416 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, 0x50, BMASK(9:0)); //CPU r/w address in Hal_HDCP22_PortInit()
3892 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
3895 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3908 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3924 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3971 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, (bEnable ? BIT(10):0), BIT(10)); // HDCP enable f… in Hal_HDCP_ddc_en()
4339 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + u16bank_offset, BIT(13), BIT(13)); // [13]: when detect no input… in Hal_HDMI_init()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 3331 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
3334 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
3413 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, BIT(10), BIT(10)); //HDCP enalbe for DDC in Hal_HDCP22_PortInit()
3416 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, 0x50, BMASK(9:0)); //CPU r/w address in Hal_HDCP22_PortInit()
3892 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
3895 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3908 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3924 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3971 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, (bEnable ? BIT(10):0), BIT(10)); // HDCP enable f… in Hal_HDCP_ddc_en()
4339 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + u16bank_offset, BIT(13), BIT(13)); // [13]: when detect no input… in Hal_HDMI_init()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 3872 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
3875 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
3964 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, BIT(10), BIT(10)); //HDCP enalbe for DDC in Hal_HDCP22_PortInit()
3967 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, 0x50, BMASK(9:0)); //CPU r/w address in Hal_HDCP22_PortInit()
4454 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
4457 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4470 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4486 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4542 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, (bEnable ? BIT(10):0), BIT(10)); // HDCP enable fo… in Hal_HDCP_ddc_en()
4913 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + u16bank_offset, BIT(13), BIT(13)); // [13]: when detect no input… in Hal_HDMI_init()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 3875 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
3878 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
3967 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, BIT(10), BIT(10)); //HDCP enalbe for DDC in Hal_HDCP22_PortInit()
3970 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, 0x50, BMASK(9:0)); //CPU r/w address in Hal_HDCP22_PortInit()
4457 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
4460 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4473 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4489 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4545 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, (bEnable ? BIT(10):0), BIT(10)); // HDCP enable fo… in Hal_HDCP_ddc_en()
4916 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + u16bank_offset, BIT(13), BIT(13)); // [13]: when detect no input… in Hal_HDMI_init()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 3875 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
3878 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
3967 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, BIT(10), BIT(10)); //HDCP enalbe for DDC in Hal_HDCP22_PortInit()
3970 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, 0x50, BMASK(9:0)); //CPU r/w address in Hal_HDCP22_PortInit()
4460 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
4463 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4476 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4492 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4548 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, (bEnable ? BIT(10):0), BIT(10)); // HDCP enable fo… in Hal_HDCP_ddc_en()
4919 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + u16bank_offset, BIT(13), BIT(13)); // [13]: when detect no input… in Hal_HDMI_init()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 3294 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, BIT(10), BIT(10)); //HDCP enalbe for DDC in Hal_HDCP22_PortInit()
3297 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, 0x50, BMASK(9:0)); //CPU r/w address in Hal_HDCP22_PortInit()
3782 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
3785 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3798 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3814 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3866 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, (bEnable ? BIT(10):0), BIT(10)); // HDCP enable fo… in Hal_HDCP_ddc_en()
4230 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + u16bank_offset, BIT(13), BIT(13)); // [13]: when detect no input… in Hal_HDMI_init()
6031 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_WriteX74()
6034 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, ubOffset, BMASK(9:0)); // address in Hal_HDCP_WriteX74()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 3324 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, BIT(10), BIT(10)); //HDCP enalbe for DDC in Hal_HDCP22_PortInit()
3327 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, 0x50, BMASK(9:0)); //CPU r/w address in Hal_HDCP22_PortInit()
3882 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
3885 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3898 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3914 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3971 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, (bEnable ? BIT(10):0), BIT(10)); // HDCP enable fo… in Hal_HDCP_ddc_en()
4337 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + u16bank_offset, BIT(13), BIT(13)); // [13]: when detect no input… in Hal_HDMI_init()
6154 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_WriteX74()
6157 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, ubOffset, BMASK(9:0)); // address in Hal_HDCP_WriteX74()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 3308 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, BIT(10), BIT(10)); //HDCP enalbe for DDC in Hal_HDCP22_PortInit()
3311 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, 0x50, BMASK(9:0)); //CPU r/w address in Hal_HDCP22_PortInit()
3827 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
3830 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3843 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3859 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3911 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, (bEnable ? BIT(10):0), BIT(10)); // HDCP enable fo… in Hal_HDCP_ddc_en()
4281 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + u16bank_offset, BIT(13), BIT(13)); // [13]: when detect no input… in Hal_HDMI_init()
6152 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_WriteX74()
6155 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, ubOffset, BMASK(9:0)); // address in Hal_HDCP_WriteX74()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 3324 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, BIT(10), BIT(10)); //HDCP enalbe for DDC in Hal_HDCP22_PortInit()
3327 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, 0x50, BMASK(9:0)); //CPU r/w address in Hal_HDCP22_PortInit()
3882 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
3885 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3898 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3914 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3971 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, (bEnable ? BIT(10):0), BIT(10)); // HDCP enable fo… in Hal_HDCP_ddc_en()
4337 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + u16bank_offset, BIT(13), BIT(13)); // [13]: when detect no input… in Hal_HDMI_init()
6154 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_WriteX74()
6157 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, ubOffset, BMASK(9:0)); // address in Hal_HDCP_WriteX74()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 1380 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, BIT(10), BIT(10)); //HDCP enalbe for DDC in Hal_HDCP22_PortInit()
1383 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x50, BMASK(9:0)); //CPU r/w address in Hal_HDCP22_PortInit()
1758 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, BIT(10), BIT(10)); // [10]: HDCP enable for DDC in Hal_HDCP_initproductionkey()
1761 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
1776 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
1820 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, (bEnable ? BIT(10):0), BIT(10)); // HDCP enable for ddc in Hal_HDCP_ddc_en()
2021 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, BIT(13), BIT(13)); // [13]: when detect no input, rest HDCP FSM t… in Hal_HDMI_init()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 3497 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, BIT(10), BIT(10)); //HDCP enalbe for DDC in Hal_HDCP22_PortInit()
3500 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, 0x50, BMASK(9:0)); //CPU r/w address in Hal_HDCP22_PortInit()
4016 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
4019 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4032 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4048 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4100 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, (bEnable ? BIT(10):0), BIT(10)); // HDCP enable fo… in Hal_HDCP_ddc_en()
4465 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + u16bank_offset, BIT(13), BIT(13)); // [13]: when detect no input… in Hal_HDMI_init()
6522 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_WriteX74()
6525 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, ubOffset, BMASK(9:0)); // address in Hal_HDCP_WriteX74()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 3497 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, BIT(10), BIT(10)); //HDCP enalbe for DDC in Hal_HDCP22_PortInit()
3500 W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + dwBKOffset, 0x50, BMASK(9:0)); //CPU r/w address in Hal_HDCP22_PortInit()
4016 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
4019 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4032 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4048 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4100 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, (bEnable ? BIT(10):0), BIT(10)); // HDCP enable fo… in Hal_HDCP_ddc_en()
4465 …W2BYTEMSK(REG_HDCP_DUAL_P0_17_L + u16bank_offset, BIT(13), BIT(13)); // [13]: when detect no input… in Hal_HDMI_init()
6522 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_WriteX74()
6525 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, ubOffset, BMASK(9:0)); // address in Hal_HDCP_WriteX74()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 3933 #define REG_HDCP_DUAL_P0_17_L (REG_HDCP_DUAL_P0_BASE + 0x2E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 3935 #define REG_HDCP_DUAL_P0_17_L (REG_HDCP_DUAL_P0_BASE + 0x2E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 3933 #define REG_HDCP_DUAL_P0_17_L (REG_HDCP_DUAL_P0_BASE + 0x2E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 3935 #define REG_HDCP_DUAL_P0_17_L (REG_HDCP_DUAL_P0_BASE + 0x2E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 3933 #define REG_HDCP_DUAL_P0_17_L (REG_HDCP_DUAL_P0_BASE + 0x2E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 3935 #define REG_HDCP_DUAL_P0_17_L (REG_HDCP_DUAL_P0_BASE + 0x2E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 3935 #define REG_HDCP_DUAL_P0_17_L (REG_HDCP_DUAL_P0_BASE + 0x2E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 3933 #define REG_HDCP_DUAL_P0_17_L (REG_HDCP_DUAL_P0_BASE + 0x2E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 3934 #define REG_HDCP_DUAL_P0_17_L (REG_HDCP_DUAL_P0_BASE + 0x2E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 3933 #define REG_HDCP_DUAL_P0_17_L (REG_HDCP_DUAL_P0_BASE + 0x2E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 3933 #define REG_HDCP_DUAL_P0_17_L (REG_HDCP_DUAL_P0_BASE + 0x2E) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 3933 #define REG_HDCP_DUAL_P0_17_L (REG_HDCP_DUAL_P0_BASE + 0x2E) macro
|