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Searched refs:REG_FSC_BK1D_0A (Results 1 – 25 of 34) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
457 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_FHD_YUV()
878 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1299 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1720 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2141 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
457 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_480.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_480_2D_480_RGB_BYPASS()
486 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_576_2D_576_RGB_BYPASS()
486 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_720_2D_720_RGB_BYPASS()
486 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_ACT_4K0_5K.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K1K_LLRR_240.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaserati_ACT_4K1K.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K2K_120.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_120.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K0_5K_LLRR_240.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K1K_120.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
457 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_FHD_YUV()
878 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1299 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1720 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2141 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
457 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_720.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_720_2D_720_RGB_BYPASS()
486 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_480_2D_480_RGB_BYPASS()
486 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_576_2D_576_RGB_BYPASS()
486 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_ACT_4K1K.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K2K_120.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K0_5K_LLRR_240.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_60.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K1K_120.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_120.c36 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A DManhattan_2D_4K2K.c35 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
503 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_FHD_YUV()
971 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1439 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_4K2K_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A DManhattan_2D_4K2K.c35 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
503 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x22, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_FHD_YUV()
971 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1439 MDrv_WriteByteMask( REG_FSC_BK1D_0A, 0x40, 0x7f); // reg_flh_last_ctr in MFC_3D_2D_4K2K_2D_4K2K_YUV()

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