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Searched refs:REG_FSC_BK1D_02 (Results 1 – 25 of 34) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
453 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_FHD_YUV()
874 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1295 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1716 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2137 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
453 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_480.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_480_2D_480_RGB_BYPASS()
482 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_576_2D_576_RGB_BYPASS()
482 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_720_2D_720_RGB_BYPASS()
482 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_ACT_4K0_5K.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K1K_LLRR_240.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaserati_ACT_4K1K.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K2K_120.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_120.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K0_5K_LLRR_240.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K1K_120.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
453 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_FHD_YUV()
874 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1295 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1716 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2137 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
453 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_720.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_720_2D_720_RGB_BYPASS()
482 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_480_2D_480_RGB_BYPASS()
482 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_576_2D_576_RGB_BYPASS()
482 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_ACT_4K1K.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K2K_120.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K0_5K_LLRR_240.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_60.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K1K_120.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_120.c32 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A DManhattan_2D_4K2K.c31 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
499 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_FHD_YUV()
967 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1435 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_4K2K_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A DManhattan_2D_4K2K.c31 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
499 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x40, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_FHD_YUV()
967 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1435 MDrv_WriteByteMask( REG_FSC_BK1D_02, 0x00, 0xff); // reg_dd_pixel_num (H) in MFC_3D_2D_4K2K_2D_4K2K_YUV()

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