Home
last modified time | relevance | path

Searched refs:REG_FSC_BK1B_10 (Results 1 – 25 of 34) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
508 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
509 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
510 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_2D_4K2K_2D_FHD_YUV()
929 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
930 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
931 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1350 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
[all …]
H A DMaserati_2D_FHD.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
508 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_FHD_2D_FHD_YUV()
509 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_FHD_2D_FHD_YUV()
510 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_480.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_480_2D_480_RGB_BYPASS()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_480_2D_480_RGB_BYPASS()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_480_2D_480_RGB_BYPASS()
537 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_480_2D_480_YUV()
538 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_480_2D_480_YUV()
539 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_576_2D_576_RGB_BYPASS()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_576_2D_576_RGB_BYPASS()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_576_2D_576_RGB_BYPASS()
537 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_576_2D_576_YUV()
538 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_576_2D_576_YUV()
539 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_720_2D_720_RGB_BYPASS()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_720_2D_720_RGB_BYPASS()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_720_2D_720_RGB_BYPASS()
537 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_720_2D_720_YUV()
538 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_720_2D_720_YUV()
539 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_ACT_4K0_5K.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K1K_LLRR_240.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaserati_ACT_4K1K.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K2K_120.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_120.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K0_5K_LLRR_240.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K1K_120.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
508 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
509 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
510 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_2D_4K2K_2D_FHD_YUV()
929 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
930 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
931 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1350 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
[all …]
H A DMaserati_2D_FHD.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
508 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_FHD_2D_FHD_YUV()
509 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_FHD_2D_FHD_YUV()
510 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_720.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_720_2D_720_RGB_BYPASS()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_720_2D_720_RGB_BYPASS()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_720_2D_720_RGB_BYPASS()
537 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_720_2D_720_YUV()
538 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_720_2D_720_YUV()
539 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_480_2D_480_RGB_BYPASS()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_480_2D_480_RGB_BYPASS()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_480_2D_480_RGB_BYPASS()
537 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_480_2D_480_YUV()
538 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_480_2D_480_YUV()
539 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_576_2D_576_RGB_BYPASS()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_576_2D_576_RGB_BYPASS()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_576_2D_576_RGB_BYPASS()
537 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_576_2D_576_YUV()
538 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_576_2D_576_YUV()
539 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_ACT_4K1K.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K2K_120.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K0_5K_LLRR_240.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_60.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K1K_120.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_120.c87 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
88 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
89 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A DManhattan_2D_4K2K.c98 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
99 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
100 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
566 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
567 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
568 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_2D_4K2K_2D_FHD_YUV()
1034 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1035 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1036 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1502 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A DManhattan_2D_4K2K.c98 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
99 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
100 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
566 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
567 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_4K2K_2D_FHD_YUV()
568 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x40); // reg_main_444to422_filter in MFC_3D_2D_4K2K_2D_FHD_YUV()
1034 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1035 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x02); // reg_main_h_mirror_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1036 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x00, 0x40); // reg_main_444to422_filter in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1502 MDrv_WriteByteMask( REG_FSC_BK1B_10, 0x41, 0x01); // reg_main_444to422_en in MFC_3D_2D_4K2K_2D_4K2K_YUV()
[all …]

12