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Searched refs:REG_FRC_BK233_31 (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
781 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_2D_4K2K_2D_FHD_YUV()
782 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_2D_4K2K_2D_FHD_YUV()
1202 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1203 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1623 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1624 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_2D_4K2K_2D_4K2K_YUV()
2044 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2045 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
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H A DMaserati_2D_FHD.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
781 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_2D_FHD_2D_FHD_YUV()
782 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_ACT_4K0_5K.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K1K_LLRR_240.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaserati_ACT_4K1K.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K2K_120.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_120.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K0_5K_LLRR_240.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x10, 0x10); // reg_mlb_mi_half_sr in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x20, 0x20); // reg_mlb_me_half_sr in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K1K_120.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_60.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A Dhwreg_frc_map.h7532 #define REG_FRC_BK233_31 (REG_FRC_BANK_BASE+0x23331) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
781 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_2D_4K2K_2D_FHD_YUV()
782 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_2D_4K2K_2D_FHD_YUV()
1202 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1203 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1623 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1624 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_2D_4K2K_2D_4K2K_YUV()
2044 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2045 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
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H A DMaserati_2D_FHD.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
781 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_2D_FHD_2D_FHD_YUV()
782 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_ACT_4K1K.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K2K_120.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K0_5K_LLRR_240.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x10, 0x10); // reg_mlb_mi_half_sr in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x20, 0x20); // reg_mlb_me_half_sr in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_60.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K1K_120.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_120.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaserati_ACT_4K0_5K.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K1K_LLRR_240.c360 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x10); // reg_mlb_mi_half_sr in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
361 MDrv_WriteByteMask( REG_FRC_BK233_31 , 0x00, 0x20); // reg_mlb_me_half_sr in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A Dhwreg_frc_map.h7532 #define REG_FRC_BK233_31 (REG_FRC_BANK_BASE+0x23331) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_frc_map.h7532 #define REG_FRC_BK233_31 (REG_FRC_BANK_BASE+0x23331) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_frc_map.h7532 #define REG_FRC_BK233_31 (REG_FRC_BANK_BASE+0x23331) macro