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Searched refs:REG_FRC_BANK_BASE (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_frc_map.h98 #define FRC_PK_L_(bank, addr) (REG_FRC_BANK_BASE + (((MS_U16)bank << 8) | (MS_U16)(addr*…
99 #define FRC_PK_H_( bank, addr) (REG_FRC_BANK_BASE + (((MS_U16)bank << 8) | (MS_U16)(addr…
4840 #define REG_FRC_BK16_00 (REG_FRC_BANK_BASE+0x1600)
4841 #define REG_FRC_BK16_01 (REG_FRC_BANK_BASE+0x1601)
4842 #define REG_FRC_BK16_02 (REG_FRC_BANK_BASE+0x1602)
4843 #define REG_FRC_BK16_03 (REG_FRC_BANK_BASE+0x1603)
4844 #define REG_FRC_BK16_04 (REG_FRC_BANK_BASE+0x1604)
4845 #define REG_FRC_BK16_05 (REG_FRC_BANK_BASE+0x1605)
4846 #define REG_FRC_BK16_06 (REG_FRC_BANK_BASE+0x1606)
4847 #define REG_FRC_BK16_07 (REG_FRC_BANK_BASE+0x1607)
[all …]
H A Dmhal_frc.h125 MDrv_WriteByte(REG_FRC_BANK_BASE, _x_)
127 MDrv_ReadByte(REG_FRC_BANK_BASE)
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_frc_map.h98 #define FRC_PK_L_(bank, addr) (REG_FRC_BANK_BASE + (((MS_U16)bank << 8) | (MS_U16)(addr*…
99 #define FRC_PK_H_( bank, addr) (REG_FRC_BANK_BASE + (((MS_U16)bank << 8) | (MS_U16)(addr…
4840 #define REG_FRC_BK16_00 (REG_FRC_BANK_BASE+0x1600)
4841 #define REG_FRC_BK16_01 (REG_FRC_BANK_BASE+0x1601)
4842 #define REG_FRC_BK16_02 (REG_FRC_BANK_BASE+0x1602)
4843 #define REG_FRC_BK16_03 (REG_FRC_BANK_BASE+0x1603)
4844 #define REG_FRC_BK16_04 (REG_FRC_BANK_BASE+0x1604)
4845 #define REG_FRC_BK16_05 (REG_FRC_BANK_BASE+0x1605)
4846 #define REG_FRC_BK16_06 (REG_FRC_BANK_BASE+0x1606)
4847 #define REG_FRC_BK16_07 (REG_FRC_BANK_BASE+0x1607)
[all …]
H A Dmhal_frc.h125 MDrv_WriteByte(REG_FRC_BANK_BASE, _x_)
127 MDrv_ReadByte(REG_FRC_BANK_BASE)
H A Dmhal_xc_chip_config.h614 #define REG_FRC_BANK_BASE 0x400000UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_frc_map.h98 #define FRC_PK_L_(bank, addr) (REG_FRC_BANK_BASE + (((MS_U16)bank << 8) | (MS_U16)(addr*…
99 #define FRC_PK_H_( bank, addr) (REG_FRC_BANK_BASE + (((MS_U16)bank << 8) | (MS_U16)(addr…
5158 #define REG_FRC_BK216_00 (REG_FRC_BANK_BASE+0x21600)
5159 #define REG_FRC_BK216_01 (REG_FRC_BANK_BASE+0x21601)
5160 #define REG_FRC_BK216_02 (REG_FRC_BANK_BASE+0x21602)
5161 #define REG_FRC_BK216_03 (REG_FRC_BANK_BASE+0x21603)
5162 #define REG_FRC_BK216_04 (REG_FRC_BANK_BASE+0x21604)
5163 #define REG_FRC_BK216_05 (REG_FRC_BANK_BASE+0x21605)
5164 #define REG_FRC_BK216_06 (REG_FRC_BANK_BASE+0x21606)
5165 #define REG_FRC_BK216_07 (REG_FRC_BANK_BASE+0x21607)
[all …]
H A Dmhal_frc.h125 MDrv_WriteByte(REG_FRC_BANK_BASE, _x_)
127 MDrv_ReadByte(REG_FRC_BANK_BASE)
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_frc_map.h98 #define FRC_PK_L_(bank, addr) (REG_FRC_BANK_BASE + (((MS_U16)bank << 8) | (MS_U16)(addr*…
99 #define FRC_PK_H_( bank, addr) (REG_FRC_BANK_BASE + (((MS_U16)bank << 8) | (MS_U16)(addr…
5158 #define REG_FRC_BK216_00 (REG_FRC_BANK_BASE+0x21600)
5159 #define REG_FRC_BK216_01 (REG_FRC_BANK_BASE+0x21601)
5160 #define REG_FRC_BK216_02 (REG_FRC_BANK_BASE+0x21602)
5161 #define REG_FRC_BK216_03 (REG_FRC_BANK_BASE+0x21603)
5162 #define REG_FRC_BK216_04 (REG_FRC_BANK_BASE+0x21604)
5163 #define REG_FRC_BK216_05 (REG_FRC_BANK_BASE+0x21605)
5164 #define REG_FRC_BK216_06 (REG_FRC_BANK_BASE+0x21606)
5165 #define REG_FRC_BK216_07 (REG_FRC_BANK_BASE+0x21607)
[all …]
H A Dmhal_frc.h125 MDrv_WriteByte(REG_FRC_BANK_BASE, _x_)
127 MDrv_ReadByte(REG_FRC_BANK_BASE)
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_frc_map.h98 #define FRC_PK_L_(bank, addr) (REG_FRC_BANK_BASE + (((MS_U16)bank << 8) | (MS_U16)(addr*…
99 #define FRC_PK_H_( bank, addr) (REG_FRC_BANK_BASE + (((MS_U16)bank << 8) | (MS_U16)(addr…
5158 #define REG_FRC_BK216_00 (REG_FRC_BANK_BASE+0x21600)
5159 #define REG_FRC_BK216_01 (REG_FRC_BANK_BASE+0x21601)
5160 #define REG_FRC_BK216_02 (REG_FRC_BANK_BASE+0x21602)
5161 #define REG_FRC_BK216_03 (REG_FRC_BANK_BASE+0x21603)
5162 #define REG_FRC_BK216_04 (REG_FRC_BANK_BASE+0x21604)
5163 #define REG_FRC_BK216_05 (REG_FRC_BANK_BASE+0x21605)
5164 #define REG_FRC_BK216_06 (REG_FRC_BANK_BASE+0x21606)
5165 #define REG_FRC_BK216_07 (REG_FRC_BANK_BASE+0x21607)
[all …]
H A Dmhal_frc.h125 MDrv_WriteByte(REG_FRC_BANK_BASE, _x_)
127 MDrv_ReadByte(REG_FRC_BANK_BASE)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_frc_map.h98 #define FRC_PK_L_(bank, addr) (REG_FRC_BANK_BASE + (((MS_U16)bank << 8) | (MS_U16)(addr*…
99 #define FRC_PK_H_( bank, addr) (REG_FRC_BANK_BASE + (((MS_U16)bank << 8) | (MS_U16)(addr…
5158 #define REG_FRC_BK216_00 (REG_FRC_BANK_BASE+0x21600)
5159 #define REG_FRC_BK216_01 (REG_FRC_BANK_BASE+0x21601)
5160 #define REG_FRC_BK216_02 (REG_FRC_BANK_BASE+0x21602)
5161 #define REG_FRC_BK216_03 (REG_FRC_BANK_BASE+0x21603)
5162 #define REG_FRC_BK216_04 (REG_FRC_BANK_BASE+0x21604)
5163 #define REG_FRC_BK216_05 (REG_FRC_BANK_BASE+0x21605)
5164 #define REG_FRC_BK216_06 (REG_FRC_BANK_BASE+0x21606)
5165 #define REG_FRC_BK216_07 (REG_FRC_BANK_BASE+0x21607)
[all …]
H A Dmhal_frc.h125 MDrv_WriteByte(REG_FRC_BANK_BASE, _x_)
127 MDrv_ReadByte(REG_FRC_BANK_BASE)
H A Dmhal_xc_chip_config.h651 #define REG_FRC_BANK_BASE 0x400000UL macro
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Dhwreg_frc.h105 #define REG_FRC_CHIP_BASE (REG_FRC_BANK_BASE+0x1E00) //REG_FRC_CHIP_BASE
107 #define REG_FRC_SC16_BASE (REG_FRC_BANK_BASE+0x1600) //REG_FRC_SC0_IP_BASE
109 #define REG_FRC_SC18_BASE (REG_FRC_BANK_BASE+0x1800) //
111 #define REG_FRC_SC20_BASE (REG_FRC_BANK_BASE+0x2000) //REG_FRC_SC0_IP_BASE
112 #define REG_FRC_SC21_BASE (REG_FRC_BANK_BASE+0x2100) //REG_FRC_SC1_VBI_BASE
113 #define REG_FRC_SC22_BASE (REG_FRC_BANK_BASE+0x2200) //REG_FRC_SC2_LVDSRX_BASE
114 #define REG_FRC_SC23_BASE (REG_FRC_BANK_BASE+0x2300) //REG_FRC_SC3_TCON_BASE
115 #define REG_FRC_SC24_BASE (REG_FRC_BANK_BASE+0x2400) //REG_FRC_SC4_SCTOP_BASE
116 #define REG_FRC_SC25_BASE (REG_FRC_BANK_BASE+0x2500) //REG_FRC_SC5_PWM_BASE
117 #define REG_FRC_SC26_BASE (REG_FRC_BANK_BASE+0x2600) //REG_FRC_SC6_MCPLUS_BASE
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_frc.h125 MDrv_WriteByte(REG_FRC_BANK_BASE, _x_)
127 MDrv_ReadByte(REG_FRC_BANK_BASE)
H A Dmhal_xc_chip_config.h571 #define REG_FRC_BANK_BASE REG_SCALER_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_frc.h125 MDrv_WriteByte(REG_FRC_BANK_BASE, _x_)
127 MDrv_ReadByte(REG_FRC_BANK_BASE)
H A Dmhal_xc_chip_config.h554 #define REG_FRC_BANK_BASE REG_SCALER_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_frc.h125 MDrv_WriteByte(REG_FRC_BANK_BASE, _x_)
127 MDrv_ReadByte(REG_FRC_BANK_BASE)
H A Dmhal_xc_chip_config.h573 #define REG_FRC_BANK_BASE REG_SCALER_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h591 #define REG_FRC_BANK_BASE (0x300000) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h597 #define REG_FRC_BANK_BASE (0x300000) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h597 #define REG_FRC_BANK_BASE (0x300000) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h599 #define REG_FRC_BANK_BASE (0x300000) macro

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