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Searched refs:REG_FIQHYP_MASK_L (Results 1 – 10 of 10) sorted by relevance

/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DhalCHIP.c518 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
563 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_EnableIRQ()
597 IRQHYP_REG(REG_FIQHYP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
646 IRQHYP_REG(REG_FIQHYP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_DisableIRQ()
1654 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1699 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_EnableIRQ()
1733 IRQHYP_REG(REG_FIQHYP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1782 IRQHYP_REG(REG_FIQHYP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h147 #define REG_FIQHYP_MASK_L (REG_INT_BASE_ADDR + 0x0004) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DhalCHIP.c518 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
563 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_EnableIRQ()
597 IRQHYP_REG(REG_FIQHYP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
646 IRQHYP_REG(REG_FIQHYP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_DisableIRQ()
1654 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1699 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_EnableIRQ()
1733 IRQHYP_REG(REG_FIQHYP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1782 IRQHYP_REG(REG_FIQHYP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h147 #define REG_FIQHYP_MASK_L (REG_INT_BASE_ADDR + 0x0004) macro
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DhalCHIP.c518 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
563 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_EnableIRQ()
597 IRQHYP_REG(REG_FIQHYP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
646 IRQHYP_REG(REG_FIQHYP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_DisableIRQ()
1641 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1686 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_EnableIRQ()
1720 IRQHYP_REG(REG_FIQHYP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1769 IRQHYP_REG(REG_FIQHYP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h147 #define REG_FIQHYP_MASK_L (REG_INT_BASE_ADDR + 0x0004) macro
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DhalCHIP.c518 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
563 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_EnableIRQ()
597 IRQHYP_REG(REG_FIQHYP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
646 IRQHYP_REG(REG_FIQHYP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_DisableIRQ()
1654 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1699 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_EnableIRQ()
1733 IRQHYP_REG(REG_FIQHYP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1782 IRQHYP_REG(REG_FIQHYP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h147 #define REG_FIQHYP_MASK_L (REG_INT_BASE_ADDR + 0x0004) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DhalCHIP.c518 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
563 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_EnableIRQ()
597 IRQHYP_REG(REG_FIQHYP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
646 IRQHYP_REG(REG_FIQHYP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_DisableIRQ()
1654 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1699 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_EnableIRQ()
1733 IRQHYP_REG(REG_FIQHYP_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1782 IRQHYP_REG(REG_FIQHYP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQHYPL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h147 #define REG_FIQHYP_MASK_L (REG_INT_BASE_ADDR + 0x0004) macro