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Searched refs:REG_FIQHYP_MASK_H (Results 1 – 10 of 10) sorted by relevance

/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DhalCHIP.c519 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
567 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_EnableIRQ()
598 IRQHYP_REG(REG_FIQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
651 IRQHYP_REG(REG_FIQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_DisableIRQ()
1655 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1703 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_EnableIRQ()
1734 IRQHYP_REG(REG_FIQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1787 IRQHYP_REG(REG_FIQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h148 #define REG_FIQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0005) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DhalCHIP.c519 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
567 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_EnableIRQ()
598 IRQHYP_REG(REG_FIQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
651 IRQHYP_REG(REG_FIQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_DisableIRQ()
1655 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1703 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_EnableIRQ()
1734 IRQHYP_REG(REG_FIQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1787 IRQHYP_REG(REG_FIQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h148 #define REG_FIQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0005) macro
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DhalCHIP.c519 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
567 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_EnableIRQ()
598 IRQHYP_REG(REG_FIQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
651 IRQHYP_REG(REG_FIQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_DisableIRQ()
1642 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1690 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_EnableIRQ()
1721 IRQHYP_REG(REG_FIQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1774 IRQHYP_REG(REG_FIQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h148 #define REG_FIQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0005) macro
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DhalCHIP.c519 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
567 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_EnableIRQ()
598 IRQHYP_REG(REG_FIQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
651 IRQHYP_REG(REG_FIQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_DisableIRQ()
1655 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1703 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_EnableIRQ()
1734 IRQHYP_REG(REG_FIQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1787 IRQHYP_REG(REG_FIQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h148 #define REG_FIQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0005) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DhalCHIP.c519 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
567 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_EnableIRQ()
598 IRQHYP_REG(REG_FIQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
651 IRQHYP_REG(REG_FIQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_DisableIRQ()
1655 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1703 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_EnableIRQ()
1734 IRQHYP_REG(REG_FIQHYP_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1787 IRQHYP_REG(REG_FIQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQHYPH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h148 #define REG_FIQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0005) macro