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Searched refs:REG_DVI_RSV_DUAL_P0_01_L (Results 1 – 15 of 15) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c3137 …W2BYTEMSK(REG_DVI_RSV_DUAL_P0_01_L+u8offset, bflag ? BMASK(9:8) : 0, BMASK(9:8)); // [9]: DE cycle… in Hal_DVI_EnhanceImmeswitch()
3154 …W2BYTEMSK(REG_DVI_RSV_DUAL_P0_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch… in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c3874 …W2BYTEMSK(REG_DVI_RSV_DUAL_P0_01_L+u8offset, bflag ? BMASK(9:8) : 0, BMASK(9:8)); // [9]: DE cycle… in Hal_DVI_EnhanceImmeswitch()
3891 …W2BYTEMSK(REG_DVI_RSV_DUAL_P0_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch… in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h3825 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h3825 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h3825 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h3825 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h3824 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02) macro