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Searched refs:REG_DVI_PS_BASE (Results 1 – 25 of 46) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h911 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00)
912 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01)
913 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02)
914 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03)
915 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04)
916 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05)
917 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06)
918 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07)
919 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) //
920 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h911 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00)
912 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01)
913 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02)
914 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03)
915 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04)
916 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05)
917 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06)
918 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07)
919 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) //
920 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00)
894 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01)
895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02)
896 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03)
897 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04)
898 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05)
899 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06)
900 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07)
901 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) //
902 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00)
894 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01)
895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02)
896 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03)
897 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04)
898 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05)
899 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06)
900 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07)
901 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) //
902 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00)
894 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01)
895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02)
896 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03)
897 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04)
898 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05)
899 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06)
900 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07)
901 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) //
902 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00)
894 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01)
895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02)
896 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03)
897 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04)
898 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05)
899 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06)
900 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07)
901 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) //
902 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00)
894 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01)
895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02)
896 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03)
897 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04)
898 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05)
899 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06)
900 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07)
901 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) //
902 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00)
894 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01)
895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02)
896 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03)
897 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04)
898 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05)
899 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06)
900 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07)
901 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) //
902 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00)
894 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01)
895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02)
896 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03)
897 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04)
898 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05)
899 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06)
900 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07)
901 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) //
902 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00)
894 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01)
895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02)
896 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03)
897 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04)
898 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05)
899 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06)
900 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07)
901 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) //
902 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00)
894 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01)
895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02)
896 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03)
897 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04)
898 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05)
899 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06)
900 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07)
901 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) //
902 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00)
894 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01)
895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02)
896 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03)
897 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04)
898 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05)
899 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06)
900 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07)
901 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) //
902 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00)
894 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01)
895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02)
896 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03)
897 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04)
898 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05)
899 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06)
900 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07)
901 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) //
902 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00)
894 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01)
895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02)
896 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03)
897 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04)
898 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05)
899 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06)
900 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07)
901 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) //
902 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00)
894 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01)
895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02)
896 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03)
897 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04)
898 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05)
899 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06)
900 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07)
901 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) //
902 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/cec/include/
H A Dcec_hwreg.h133 #define REG_DVI_PS_BASE 0x113600UL // DVI power saving macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/cec/include/
H A Dcec_hwreg.h133 #define REG_DVI_PS_BASE 0x113600UL // DVI power saving macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/cec/include/
H A Dcec_hwreg.h133 #define REG_DVI_PS_BASE 0x113600UL // DVI power saving macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/cec/include/
H A Dcec_hwreg.h133 #define REG_DVI_PS_BASE 0x113600 // DVI power saving macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/cec/include/
H A Dcec_hwreg.h133 #define REG_DVI_PS_BASE 0x113600UL // DVI power saving macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/cec/include/
H A Dcec_hwreg.h133 #define REG_DVI_PS_BASE 0x113600UL // DVI power saving macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/cec/include/
H A Dcec_hwreg.h133 #define REG_DVI_PS_BASE 0x113600UL // DVI power saving macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/cec/include/
H A Dcec_hwreg.h133 #define REG_DVI_PS_BASE 0x113600UL // DVI power saving macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/cec/include/
H A Dcec_hwreg.h133 #define REG_DVI_PS_BASE 0x113600UL // DVI power saving macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/cec/include/
H A Dcec_hwreg.h133 #define REG_DVI_PS_BASE 0x113600 // DVI power saving macro

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