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Searched refs:REG_DVI_PS_01_L (Results 1 – 25 of 32) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_mux.c250 …W2BYTEMSK(REG_DVI_PS_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE as D… in Hal_SC_mux_set_dvi_mux()
252 …W2BYTEMSK(REG_DVI_PS_01_L, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE… in Hal_SC_mux_set_dvi_mux()
253 …W2BYTEMSK(REG_DVI_PS_01_L, BMASK(9:8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch… in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c1112 … W2BYTEMSK(REG_DVI_PS_01_L+(i*u8reg_offset), BMASK(3:2), BMASK(3:0)); //[3:2]: turn off B/G. in Hal_HDMI_init()
2415 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no … in Hal_DVI_IMMESWITCH_PS_SW_Path()
2417 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(9)|BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [… in Hal_DVI_IMMESWITCH_PS_SW_Path()
2686 …W2BYTEMSK(REG_DVI_PS_01_L+u8offset, bflag ? BMASK(9:8) : 0, BMASK(9:8)); // [9]: DE cycle align de… in Hal_DVI_EnhanceImmeswitch()
2710 …W2BYTEMSK(REG_DVI_PS_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE as D… in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_mux.c250 …W2BYTEMSK(REG_DVI_PS_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE as D… in Hal_SC_mux_set_dvi_mux()
252 …W2BYTEMSK(REG_DVI_PS_01_L, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE… in Hal_SC_mux_set_dvi_mux()
253 …W2BYTEMSK(REG_DVI_PS_01_L, BMASK(9:8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch… in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c1112 … W2BYTEMSK(REG_DVI_PS_01_L+(i*u8reg_offset), BMASK(3:2), BMASK(3:0)); //[3:2]: turn off B/G. in Hal_HDMI_init()
2415 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no … in Hal_DVI_IMMESWITCH_PS_SW_Path()
2417 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(9)|BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [… in Hal_DVI_IMMESWITCH_PS_SW_Path()
2686 …W2BYTEMSK(REG_DVI_PS_01_L+u8offset, bflag ? BMASK(9:8) : 0, BMASK(9:8)); // [9]: DE cycle align de… in Hal_DVI_EnhanceImmeswitch()
2710 …W2BYTEMSK(REG_DVI_PS_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE as D… in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c5232 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5234 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(9)|BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5509 …W2BYTEMSK(REG_DVI_PS_01_L+u8offset, bflag ? BMASK(9:8) : 0, BMASK(9:8)); // [9]: DE cycle align de… in Hal_DVI_EnhanceImmeswitch()
5545 …W2BYTEMSK(REG_DVI_PS_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE as D… in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c5332 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5334 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(9)|BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5584 …W2BYTEMSK(REG_DVI_PS_01_L+u8offset, bflag ? BMASK(9:8) : 0, BMASK(9:8)); // [9]: DE cycle align de… in Hal_DVI_EnhanceImmeswitch()
5620 …W2BYTEMSK(REG_DVI_PS_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE as D… in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c5374 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5376 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(9)|BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5663 …W2BYTEMSK(REG_DVI_PS_01_L+u8offset, bflag ? BMASK(9:8) : 0, BMASK(9:8)); // [9]: DE cycle align de… in Hal_DVI_EnhanceImmeswitch()
5699 …W2BYTEMSK(REG_DVI_PS_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE as D… in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c5332 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5334 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(9)|BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5584 …W2BYTEMSK(REG_DVI_PS_01_L+u8offset, bflag ? BMASK(9:8) : 0, BMASK(9:8)); // [9]: DE cycle align de… in Hal_DVI_EnhanceImmeswitch()
5620 …W2BYTEMSK(REG_DVI_PS_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE as D… in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c5347 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5349 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(9)|BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5624 …W2BYTEMSK(REG_DVI_PS_01_L+u8offset, bflag ? BMASK(9:8) : 0, BMASK(9:8)); // [9]: DE cycle align de… in Hal_DVI_EnhanceImmeswitch()
5660 …W2BYTEMSK(REG_DVI_PS_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE as D… in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c5374 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5376 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(9)|BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5663 …W2BYTEMSK(REG_DVI_PS_01_L+u8offset, bflag ? BMASK(9:8) : 0, BMASK(9:8)); // [9]: DE cycle align de… in Hal_DVI_EnhanceImmeswitch()
5699 …W2BYTEMSK(REG_DVI_PS_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE as D… in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c5935 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5937 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(9)|BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [… in Hal_DVI_IMMESWITCH_PS_SW_Path()
6212 …W2BYTEMSK(REG_DVI_PS_01_L+u8offset, bflag ? BMASK(9:8) : 0, BMASK(9:8)); // [9]: DE cycle align de… in Hal_DVI_EnhanceImmeswitch()
6248 …W2BYTEMSK(REG_DVI_PS_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE as D… in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c5938 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5940 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(9)|BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [… in Hal_DVI_IMMESWITCH_PS_SW_Path()
6215 …W2BYTEMSK(REG_DVI_PS_01_L+u8offset, bflag ? BMASK(9:8) : 0, BMASK(9:8)); // [9]: DE cycle align de… in Hal_DVI_EnhanceImmeswitch()
6251 …W2BYTEMSK(REG_DVI_PS_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE as D… in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c5645 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5647 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(9)|BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5930 …W2BYTEMSK(REG_DVI_PS_01_L+u8offset, bflag ? BMASK(9:8) : 0, BMASK(9:8)); // [9]: DE cycle align de… in Hal_DVI_EnhanceImmeswitch()
5966 …W2BYTEMSK(REG_DVI_PS_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE as D… in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c5941 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5943 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(9)|BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [… in Hal_DVI_IMMESWITCH_PS_SW_Path()
6218 …W2BYTEMSK(REG_DVI_PS_01_L+u8offset, bflag ? BMASK(9:8) : 0, BMASK(9:8)); // [9]: DE cycle align de… in Hal_DVI_EnhanceImmeswitch()
6254 …W2BYTEMSK(REG_DVI_PS_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE as D… in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c5645 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5647 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(9)|BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [… in Hal_DVI_IMMESWITCH_PS_SW_Path()
5930 …W2BYTEMSK(REG_DVI_PS_01_L+u8offset, bflag ? BMASK(9:8) : 0, BMASK(9:8)); // [9]: DE cycle align de… in Hal_DVI_EnhanceImmeswitch()
5966 …W2BYTEMSK(REG_DVI_PS_01_L, 0, BMASK(9:8)); //[9]: DE cycle align delay, [8]: no select Ch2 DE as D… in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c2877 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no … in Hal_DVI_IMMESWITCH_PS_SW_Path()
2879 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(9)|BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [… in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c3614 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [8]: no … in Hal_DVI_IMMESWITCH_PS_SW_Path()
3616 …W2BYTEMSK(REG_DVI_PS_01_L+u8reg_offset, BIT(9)|BIT(8), BMASK(9:8)); //[9]: DE cycle align delay, [… in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h913 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h913 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02) macro

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