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Searched refs:REG_DVI_PS_00_L (Results 1 – 25 of 32) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_mux.c243 W2BYTEMSK(REG_DVI_PS_00_L, 0, BIT(0)); // turn off DVI power saving mode in Hal_SC_mux_set_dvi_mux()
280 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI1 power saving mode in Hal_SC_mux_set_dvi_mux()
317 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI2 power saving mode in Hal_SC_mux_set_dvi_mux()
353 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI3 power saving mode in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c2420 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
2422 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, BIT(9), BIT(9)); //[9]: PS FSM reset in Hal_DVI_IMMESWITCH_PS_SW_Path()
2424 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, 0, BIT(9)); in Hal_DVI_IMMESWITCH_PS_SW_Path()
2640 result = (R2BYTEMSK(REG_DVI_PS_00_L+u8offset, BIT(0)) & BIT(0)) ? TRUE : FALSE; in Hal_DVI_GetPowerSavingStatus()
2705 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI power saving mode in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_mux.c243 W2BYTEMSK(REG_DVI_PS_00_L, 0, BIT(0)); // turn off DVI power saving mode in Hal_SC_mux_set_dvi_mux()
280 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI1 power saving mode in Hal_SC_mux_set_dvi_mux()
317 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI2 power saving mode in Hal_SC_mux_set_dvi_mux()
353 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI3 power saving mode in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c2420 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
2422 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, BIT(9), BIT(9)); //[9]: PS FSM reset in Hal_DVI_IMMESWITCH_PS_SW_Path()
2424 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, 0, BIT(9)); in Hal_DVI_IMMESWITCH_PS_SW_Path()
2640 result = (R2BYTEMSK(REG_DVI_PS_00_L+u8offset, BIT(0)) & BIT(0)) ? TRUE : FALSE; in Hal_DVI_GetPowerSavingStatus()
2705 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI power saving mode in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c2882 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
2884 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, BIT(9), BIT(9)); //[9]: PS FSM reset in Hal_DVI_IMMESWITCH_PS_SW_Path()
2886 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, 0, BIT(9)); in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c5237 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5239 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, BIT(9), BIT(9)); //[9]: PS FSM reset in Hal_DVI_IMMESWITCH_PS_SW_Path()
5241 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, 0, BIT(9)); in Hal_DVI_IMMESWITCH_PS_SW_Path()
5463 result = (R2BYTEMSK(REG_DVI_PS_00_L+u8offset, BIT(0)) & BIT(0)) ? TRUE : FALSE; in Hal_DVI_GetPowerSavingStatus()
5540 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI power saving mode in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c5337 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5339 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, BIT(9), BIT(9)); //[9]: PS FSM reset in Hal_DVI_IMMESWITCH_PS_SW_Path()
5341 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, 0, BIT(9)); in Hal_DVI_IMMESWITCH_PS_SW_Path()
5556 result = (R2BYTEMSK(REG_DVI_PS_00_L+u8offset, BIT(0)) & BIT(0)) ? TRUE : FALSE; in Hal_DVI_GetPowerSavingStatus()
5615 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI power saving mode in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c5379 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5381 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, BIT(9), BIT(9)); //[9]: PS FSM reset in Hal_DVI_IMMESWITCH_PS_SW_Path()
5383 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, 0, BIT(9)); in Hal_DVI_IMMESWITCH_PS_SW_Path()
5607 result = (R2BYTEMSK(REG_DVI_PS_00_L+u8offset, BIT(0)) & BIT(0)) ? TRUE : FALSE; in Hal_DVI_GetPowerSavingStatus()
5694 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI power saving mode in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c5337 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5339 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, BIT(9), BIT(9)); //[9]: PS FSM reset in Hal_DVI_IMMESWITCH_PS_SW_Path()
5341 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, 0, BIT(9)); in Hal_DVI_IMMESWITCH_PS_SW_Path()
5556 result = (R2BYTEMSK(REG_DVI_PS_00_L+u8offset, BIT(0)) & BIT(0)) ? TRUE : FALSE; in Hal_DVI_GetPowerSavingStatus()
5615 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI power saving mode in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c5352 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5354 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, BIT(9), BIT(9)); //[9]: PS FSM reset in Hal_DVI_IMMESWITCH_PS_SW_Path()
5356 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, 0, BIT(9)); in Hal_DVI_IMMESWITCH_PS_SW_Path()
5578 result = (R2BYTEMSK(REG_DVI_PS_00_L+u8offset, BIT(0)) & BIT(0)) ? TRUE : FALSE; in Hal_DVI_GetPowerSavingStatus()
5655 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI power saving mode in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c5379 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5381 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, BIT(9), BIT(9)); //[9]: PS FSM reset in Hal_DVI_IMMESWITCH_PS_SW_Path()
5383 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, 0, BIT(9)); in Hal_DVI_IMMESWITCH_PS_SW_Path()
5607 result = (R2BYTEMSK(REG_DVI_PS_00_L+u8offset, BIT(0)) & BIT(0)) ? TRUE : FALSE; in Hal_DVI_GetPowerSavingStatus()
5694 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI power saving mode in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c5940 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5942 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, BIT(9), BIT(9)); //[9]: PS FSM reset in Hal_DVI_IMMESWITCH_PS_SW_Path()
5944 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, 0, BIT(9)); in Hal_DVI_IMMESWITCH_PS_SW_Path()
6166 result = (R2BYTEMSK(REG_DVI_PS_00_L+u8offset, BIT(0)) & BIT(0)) ? TRUE : FALSE; in Hal_DVI_GetPowerSavingStatus()
6243 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI power saving mode in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c5943 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5945 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, BIT(9), BIT(9)); //[9]: PS FSM reset in Hal_DVI_IMMESWITCH_PS_SW_Path()
5947 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, 0, BIT(9)); in Hal_DVI_IMMESWITCH_PS_SW_Path()
6169 result = (R2BYTEMSK(REG_DVI_PS_00_L+u8offset, BIT(0)) & BIT(0)) ? TRUE : FALSE; in Hal_DVI_GetPowerSavingStatus()
6246 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI power saving mode in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c5650 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5652 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, BIT(9), BIT(9)); //[9]: PS FSM reset in Hal_DVI_IMMESWITCH_PS_SW_Path()
5654 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, 0, BIT(9)); in Hal_DVI_IMMESWITCH_PS_SW_Path()
5884 result = (R2BYTEMSK(REG_DVI_PS_00_L+u8offset, BIT(0)) & BIT(0)) ? TRUE : FALSE; in Hal_DVI_GetPowerSavingStatus()
5961 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI power saving mode in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c5946 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5948 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, BIT(9), BIT(9)); //[9]: PS FSM reset in Hal_DVI_IMMESWITCH_PS_SW_Path()
5950 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, 0, BIT(9)); in Hal_DVI_IMMESWITCH_PS_SW_Path()
6172 result = (R2BYTEMSK(REG_DVI_PS_00_L+u8offset, BIT(0)) & BIT(0)) ? TRUE : FALSE; in Hal_DVI_GetPowerSavingStatus()
6249 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI power saving mode in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c5650 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
5652 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, BIT(9), BIT(9)); //[9]: PS FSM reset in Hal_DVI_IMMESWITCH_PS_SW_Path()
5654 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, 0, BIT(9)); in Hal_DVI_IMMESWITCH_PS_SW_Path()
5884 result = (R2BYTEMSK(REG_DVI_PS_00_L+u8offset, BIT(0)) & BIT(0)) ? TRUE : FALSE; in Hal_DVI_GetPowerSavingStatus()
5961 W2BYTEMSK(REG_DVI_PS_00_L, BIT(0), BIT(0)); // turn on DVI power saving mode in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c3619 …if( !(R2BYTE(REG_DVI_PS_00_L+u8reg_offset) & BIT(0)) && (R2BYTE(REG_DVI_DTOP_31_L+u16bank_offset) … in Hal_DVI_IMMESWITCH_PS_SW_Path()
3621 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, BIT(9), BIT(9)); //[9]: PS FSM reset in Hal_DVI_IMMESWITCH_PS_SW_Path()
3623 W2BYTEMSK(REG_DVI_PS_00_L+u8reg_offset, 0, BIT(9)); in Hal_DVI_IMMESWITCH_PS_SW_Path()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h911 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h911 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00) macro

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