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Searched refs:REG_DVI_EQ3_BASE (Results 1 – 25 of 46) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h513 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
514 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
515 #define REG_DVI_EQ3_01_L (REG_DVI_EQ3_BASE + 0x02)
516 #define REG_DVI_EQ3_01_H (REG_DVI_EQ3_BASE + 0x03)
517 #define REG_DVI_EQ3_02_L (REG_DVI_EQ3_BASE + 0x04)
518 #define REG_DVI_EQ3_02_H (REG_DVI_EQ3_BASE + 0x05)
519 #define REG_DVI_EQ3_04_L (REG_DVI_EQ3_BASE + 0x08)
520 #define REG_DVI_EQ3_04_H (REG_DVI_EQ3_BASE + 0x09)
521 #define REG_DVI_EQ3_10_L (REG_DVI_EQ3_BASE + 0x20)
522 #define REG_DVI_EQ3_10_H (REG_DVI_EQ3_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h513 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
514 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
515 #define REG_DVI_EQ3_01_L (REG_DVI_EQ3_BASE + 0x02)
516 #define REG_DVI_EQ3_01_H (REG_DVI_EQ3_BASE + 0x03)
517 #define REG_DVI_EQ3_02_L (REG_DVI_EQ3_BASE + 0x04)
518 #define REG_DVI_EQ3_02_H (REG_DVI_EQ3_BASE + 0x05)
519 #define REG_DVI_EQ3_04_L (REG_DVI_EQ3_BASE + 0x08)
520 #define REG_DVI_EQ3_04_H (REG_DVI_EQ3_BASE + 0x09)
521 #define REG_DVI_EQ3_10_L (REG_DVI_EQ3_BASE + 0x20)
522 #define REG_DVI_EQ3_10_H (REG_DVI_EQ3_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/cec/include/
H A Dcec_hwreg.h135 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 macro
159 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
160 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/cec/include/
H A Dcec_hwreg.h135 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 macro
159 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
160 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/cec/include/
H A Dcec_hwreg.h135 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 macro
159 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
160 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/cec/include/
H A Dcec_hwreg.h135 #define REG_DVI_EQ3_BASE 0x113780 // EQ started from 0x80 macro
156 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
157 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/cec/include/
H A Dcec_hwreg.h135 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 macro
159 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
160 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/cec/include/
H A Dcec_hwreg.h135 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 macro
159 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
160 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/cec/include/
H A Dcec_hwreg.h135 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 macro
159 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
160 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/cec/include/
H A Dcec_hwreg.h135 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 macro
159 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
160 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/cec/include/
H A Dcec_hwreg.h135 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 macro
159 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
160 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/cec/include/
H A Dcec_hwreg.h135 #define REG_DVI_EQ3_BASE 0x113780 // EQ started from 0x80 macro
156 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
157 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/cec/include/
H A Dcec_hwreg.h135 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 macro
159 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
160 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/cec/include/
H A Dcec_hwreg.h135 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 macro
159 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
160 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/cec/include/
H A Dcec_hwreg.h135 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 macro
159 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
160 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/cec/include/
H A Dcec_hwreg.h135 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 macro
159 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
160 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/cec/include/
H A Dcec_hwreg.h135 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 macro
159 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
160 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h507 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
508 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
509 #define REG_DVI_EQ3_01_L (REG_DVI_EQ3_BASE + 0x02)
510 #define REG_DVI_EQ3_01_H (REG_DVI_EQ3_BASE + 0x03)
511 #define REG_DVI_EQ3_02_L (REG_DVI_EQ3_BASE + 0x04)
512 #define REG_DVI_EQ3_02_H (REG_DVI_EQ3_BASE + 0x05)
513 #define REG_DVI_EQ3_04_L (REG_DVI_EQ3_BASE + 0x08)
514 #define REG_DVI_EQ3_04_H (REG_DVI_EQ3_BASE + 0x09)
515 #define REG_DVI_EQ3_10_L (REG_DVI_EQ3_BASE + 0x20)
516 #define REG_DVI_EQ3_10_H (REG_DVI_EQ3_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h507 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
508 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
509 #define REG_DVI_EQ3_01_L (REG_DVI_EQ3_BASE + 0x02)
510 #define REG_DVI_EQ3_01_H (REG_DVI_EQ3_BASE + 0x03)
511 #define REG_DVI_EQ3_02_L (REG_DVI_EQ3_BASE + 0x04)
512 #define REG_DVI_EQ3_02_H (REG_DVI_EQ3_BASE + 0x05)
513 #define REG_DVI_EQ3_04_L (REG_DVI_EQ3_BASE + 0x08)
514 #define REG_DVI_EQ3_04_H (REG_DVI_EQ3_BASE + 0x09)
515 #define REG_DVI_EQ3_10_L (REG_DVI_EQ3_BASE + 0x20)
516 #define REG_DVI_EQ3_10_H (REG_DVI_EQ3_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h507 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
508 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
509 #define REG_DVI_EQ3_01_L (REG_DVI_EQ3_BASE + 0x02)
510 #define REG_DVI_EQ3_01_H (REG_DVI_EQ3_BASE + 0x03)
511 #define REG_DVI_EQ3_02_L (REG_DVI_EQ3_BASE + 0x04)
512 #define REG_DVI_EQ3_02_H (REG_DVI_EQ3_BASE + 0x05)
513 #define REG_DVI_EQ3_04_L (REG_DVI_EQ3_BASE + 0x08)
514 #define REG_DVI_EQ3_04_H (REG_DVI_EQ3_BASE + 0x09)
515 #define REG_DVI_EQ3_10_L (REG_DVI_EQ3_BASE + 0x20)
516 #define REG_DVI_EQ3_10_H (REG_DVI_EQ3_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h507 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
508 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
509 #define REG_DVI_EQ3_01_L (REG_DVI_EQ3_BASE + 0x02)
510 #define REG_DVI_EQ3_01_H (REG_DVI_EQ3_BASE + 0x03)
511 #define REG_DVI_EQ3_02_L (REG_DVI_EQ3_BASE + 0x04)
512 #define REG_DVI_EQ3_02_H (REG_DVI_EQ3_BASE + 0x05)
513 #define REG_DVI_EQ3_04_L (REG_DVI_EQ3_BASE + 0x08)
514 #define REG_DVI_EQ3_04_H (REG_DVI_EQ3_BASE + 0x09)
515 #define REG_DVI_EQ3_10_L (REG_DVI_EQ3_BASE + 0x20)
516 #define REG_DVI_EQ3_10_H (REG_DVI_EQ3_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h507 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
508 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
509 #define REG_DVI_EQ3_01_L (REG_DVI_EQ3_BASE + 0x02)
510 #define REG_DVI_EQ3_01_H (REG_DVI_EQ3_BASE + 0x03)
511 #define REG_DVI_EQ3_02_L (REG_DVI_EQ3_BASE + 0x04)
512 #define REG_DVI_EQ3_02_H (REG_DVI_EQ3_BASE + 0x05)
513 #define REG_DVI_EQ3_04_L (REG_DVI_EQ3_BASE + 0x08)
514 #define REG_DVI_EQ3_04_H (REG_DVI_EQ3_BASE + 0x09)
515 #define REG_DVI_EQ3_10_L (REG_DVI_EQ3_BASE + 0x20)
516 #define REG_DVI_EQ3_10_H (REG_DVI_EQ3_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h507 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
508 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
509 #define REG_DVI_EQ3_01_L (REG_DVI_EQ3_BASE + 0x02)
510 #define REG_DVI_EQ3_01_H (REG_DVI_EQ3_BASE + 0x03)
511 #define REG_DVI_EQ3_02_L (REG_DVI_EQ3_BASE + 0x04)
512 #define REG_DVI_EQ3_02_H (REG_DVI_EQ3_BASE + 0x05)
513 #define REG_DVI_EQ3_04_L (REG_DVI_EQ3_BASE + 0x08)
514 #define REG_DVI_EQ3_04_H (REG_DVI_EQ3_BASE + 0x09)
515 #define REG_DVI_EQ3_10_L (REG_DVI_EQ3_BASE + 0x20)
516 #define REG_DVI_EQ3_10_H (REG_DVI_EQ3_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h507 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
508 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
509 #define REG_DVI_EQ3_01_L (REG_DVI_EQ3_BASE + 0x02)
510 #define REG_DVI_EQ3_01_H (REG_DVI_EQ3_BASE + 0x03)
511 #define REG_DVI_EQ3_02_L (REG_DVI_EQ3_BASE + 0x04)
512 #define REG_DVI_EQ3_02_H (REG_DVI_EQ3_BASE + 0x05)
513 #define REG_DVI_EQ3_04_L (REG_DVI_EQ3_BASE + 0x08)
514 #define REG_DVI_EQ3_04_H (REG_DVI_EQ3_BASE + 0x09)
515 #define REG_DVI_EQ3_10_L (REG_DVI_EQ3_BASE + 0x20)
516 #define REG_DVI_EQ3_10_H (REG_DVI_EQ3_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h507 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00)
508 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01)
509 #define REG_DVI_EQ3_01_L (REG_DVI_EQ3_BASE + 0x02)
510 #define REG_DVI_EQ3_01_H (REG_DVI_EQ3_BASE + 0x03)
511 #define REG_DVI_EQ3_02_L (REG_DVI_EQ3_BASE + 0x04)
512 #define REG_DVI_EQ3_02_H (REG_DVI_EQ3_BASE + 0x05)
513 #define REG_DVI_EQ3_04_L (REG_DVI_EQ3_BASE + 0x08)
514 #define REG_DVI_EQ3_04_H (REG_DVI_EQ3_BASE + 0x09)
515 #define REG_DVI_EQ3_10_L (REG_DVI_EQ3_BASE + 0x20)
516 #define REG_DVI_EQ3_10_H (REG_DVI_EQ3_BASE + 0x21)
[all …]

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