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Searched refs:REG_DVI_EQ2_BASE (Results 1 – 25 of 46) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h495 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
496 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
497 #define REG_DVI_EQ2_01_L (REG_DVI_EQ2_BASE + 0x02)
498 #define REG_DVI_EQ2_01_H (REG_DVI_EQ2_BASE + 0x03)
499 #define REG_DVI_EQ2_02_L (REG_DVI_EQ2_BASE + 0x04)
500 #define REG_DVI_EQ2_02_H (REG_DVI_EQ2_BASE + 0x05)
501 #define REG_DVI_EQ2_04_L (REG_DVI_EQ2_BASE + 0x08)
502 #define REG_DVI_EQ2_04_H (REG_DVI_EQ2_BASE + 0x09)
503 #define REG_DVI_EQ2_10_L (REG_DVI_EQ2_BASE + 0x20)
504 #define REG_DVI_EQ2_10_H (REG_DVI_EQ2_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h495 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
496 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
497 #define REG_DVI_EQ2_01_L (REG_DVI_EQ2_BASE + 0x02)
498 #define REG_DVI_EQ2_01_H (REG_DVI_EQ2_BASE + 0x03)
499 #define REG_DVI_EQ2_02_L (REG_DVI_EQ2_BASE + 0x04)
500 #define REG_DVI_EQ2_02_H (REG_DVI_EQ2_BASE + 0x05)
501 #define REG_DVI_EQ2_04_L (REG_DVI_EQ2_BASE + 0x08)
502 #define REG_DVI_EQ2_04_H (REG_DVI_EQ2_BASE + 0x09)
503 #define REG_DVI_EQ2_10_L (REG_DVI_EQ2_BASE + 0x20)
504 #define REG_DVI_EQ2_10_H (REG_DVI_EQ2_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/cec/include/
H A Dcec_hwreg.h131 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 macro
157 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
158 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/cec/include/
H A Dcec_hwreg.h131 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 macro
157 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
158 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/cec/include/
H A Dcec_hwreg.h131 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 macro
157 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
158 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/cec/include/
H A Dcec_hwreg.h131 #define REG_DVI_EQ2_BASE 0x113580 // EQ started from 0x80 macro
154 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
155 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/cec/include/
H A Dcec_hwreg.h131 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 macro
157 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
158 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/cec/include/
H A Dcec_hwreg.h131 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 macro
157 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
158 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/cec/include/
H A Dcec_hwreg.h131 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 macro
157 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
158 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/cec/include/
H A Dcec_hwreg.h131 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 macro
157 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
158 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/cec/include/
H A Dcec_hwreg.h131 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 macro
157 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
158 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/cec/include/
H A Dcec_hwreg.h131 #define REG_DVI_EQ2_BASE 0x113580 // EQ started from 0x80 macro
154 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
155 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/cec/include/
H A Dcec_hwreg.h131 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 macro
157 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
158 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/cec/include/
H A Dcec_hwreg.h131 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 macro
157 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
158 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/cec/include/
H A Dcec_hwreg.h131 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 macro
157 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
158 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/cec/include/
H A Dcec_hwreg.h131 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 macro
157 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
158 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/cec/include/
H A Dcec_hwreg.h131 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 macro
157 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
158 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h489 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
490 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
491 #define REG_DVI_EQ2_01_L (REG_DVI_EQ2_BASE + 0x02)
492 #define REG_DVI_EQ2_01_H (REG_DVI_EQ2_BASE + 0x03)
493 #define REG_DVI_EQ2_02_L (REG_DVI_EQ2_BASE + 0x04)
494 #define REG_DVI_EQ2_02_H (REG_DVI_EQ2_BASE + 0x05)
495 #define REG_DVI_EQ2_04_L (REG_DVI_EQ2_BASE + 0x08)
496 #define REG_DVI_EQ2_04_H (REG_DVI_EQ2_BASE + 0x09)
497 #define REG_DVI_EQ2_10_L (REG_DVI_EQ2_BASE + 0x20)
498 #define REG_DVI_EQ2_10_H (REG_DVI_EQ2_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h489 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
490 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
491 #define REG_DVI_EQ2_01_L (REG_DVI_EQ2_BASE + 0x02)
492 #define REG_DVI_EQ2_01_H (REG_DVI_EQ2_BASE + 0x03)
493 #define REG_DVI_EQ2_02_L (REG_DVI_EQ2_BASE + 0x04)
494 #define REG_DVI_EQ2_02_H (REG_DVI_EQ2_BASE + 0x05)
495 #define REG_DVI_EQ2_04_L (REG_DVI_EQ2_BASE + 0x08)
496 #define REG_DVI_EQ2_04_H (REG_DVI_EQ2_BASE + 0x09)
497 #define REG_DVI_EQ2_10_L (REG_DVI_EQ2_BASE + 0x20)
498 #define REG_DVI_EQ2_10_H (REG_DVI_EQ2_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h489 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
490 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
491 #define REG_DVI_EQ2_01_L (REG_DVI_EQ2_BASE + 0x02)
492 #define REG_DVI_EQ2_01_H (REG_DVI_EQ2_BASE + 0x03)
493 #define REG_DVI_EQ2_02_L (REG_DVI_EQ2_BASE + 0x04)
494 #define REG_DVI_EQ2_02_H (REG_DVI_EQ2_BASE + 0x05)
495 #define REG_DVI_EQ2_04_L (REG_DVI_EQ2_BASE + 0x08)
496 #define REG_DVI_EQ2_04_H (REG_DVI_EQ2_BASE + 0x09)
497 #define REG_DVI_EQ2_10_L (REG_DVI_EQ2_BASE + 0x20)
498 #define REG_DVI_EQ2_10_H (REG_DVI_EQ2_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h489 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
490 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
491 #define REG_DVI_EQ2_01_L (REG_DVI_EQ2_BASE + 0x02)
492 #define REG_DVI_EQ2_01_H (REG_DVI_EQ2_BASE + 0x03)
493 #define REG_DVI_EQ2_02_L (REG_DVI_EQ2_BASE + 0x04)
494 #define REG_DVI_EQ2_02_H (REG_DVI_EQ2_BASE + 0x05)
495 #define REG_DVI_EQ2_04_L (REG_DVI_EQ2_BASE + 0x08)
496 #define REG_DVI_EQ2_04_H (REG_DVI_EQ2_BASE + 0x09)
497 #define REG_DVI_EQ2_10_L (REG_DVI_EQ2_BASE + 0x20)
498 #define REG_DVI_EQ2_10_H (REG_DVI_EQ2_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h489 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
490 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
491 #define REG_DVI_EQ2_01_L (REG_DVI_EQ2_BASE + 0x02)
492 #define REG_DVI_EQ2_01_H (REG_DVI_EQ2_BASE + 0x03)
493 #define REG_DVI_EQ2_02_L (REG_DVI_EQ2_BASE + 0x04)
494 #define REG_DVI_EQ2_02_H (REG_DVI_EQ2_BASE + 0x05)
495 #define REG_DVI_EQ2_04_L (REG_DVI_EQ2_BASE + 0x08)
496 #define REG_DVI_EQ2_04_H (REG_DVI_EQ2_BASE + 0x09)
497 #define REG_DVI_EQ2_10_L (REG_DVI_EQ2_BASE + 0x20)
498 #define REG_DVI_EQ2_10_H (REG_DVI_EQ2_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h489 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
490 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
491 #define REG_DVI_EQ2_01_L (REG_DVI_EQ2_BASE + 0x02)
492 #define REG_DVI_EQ2_01_H (REG_DVI_EQ2_BASE + 0x03)
493 #define REG_DVI_EQ2_02_L (REG_DVI_EQ2_BASE + 0x04)
494 #define REG_DVI_EQ2_02_H (REG_DVI_EQ2_BASE + 0x05)
495 #define REG_DVI_EQ2_04_L (REG_DVI_EQ2_BASE + 0x08)
496 #define REG_DVI_EQ2_04_H (REG_DVI_EQ2_BASE + 0x09)
497 #define REG_DVI_EQ2_10_L (REG_DVI_EQ2_BASE + 0x20)
498 #define REG_DVI_EQ2_10_H (REG_DVI_EQ2_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h489 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
490 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
491 #define REG_DVI_EQ2_01_L (REG_DVI_EQ2_BASE + 0x02)
492 #define REG_DVI_EQ2_01_H (REG_DVI_EQ2_BASE + 0x03)
493 #define REG_DVI_EQ2_02_L (REG_DVI_EQ2_BASE + 0x04)
494 #define REG_DVI_EQ2_02_H (REG_DVI_EQ2_BASE + 0x05)
495 #define REG_DVI_EQ2_04_L (REG_DVI_EQ2_BASE + 0x08)
496 #define REG_DVI_EQ2_04_H (REG_DVI_EQ2_BASE + 0x09)
497 #define REG_DVI_EQ2_10_L (REG_DVI_EQ2_BASE + 0x20)
498 #define REG_DVI_EQ2_10_H (REG_DVI_EQ2_BASE + 0x21)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h489 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00)
490 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01)
491 #define REG_DVI_EQ2_01_L (REG_DVI_EQ2_BASE + 0x02)
492 #define REG_DVI_EQ2_01_H (REG_DVI_EQ2_BASE + 0x03)
493 #define REG_DVI_EQ2_02_L (REG_DVI_EQ2_BASE + 0x04)
494 #define REG_DVI_EQ2_02_H (REG_DVI_EQ2_BASE + 0x05)
495 #define REG_DVI_EQ2_04_L (REG_DVI_EQ2_BASE + 0x08)
496 #define REG_DVI_EQ2_04_H (REG_DVI_EQ2_BASE + 0x09)
497 #define REG_DVI_EQ2_10_L (REG_DVI_EQ2_BASE + 0x20)
498 #define REG_DVI_EQ2_10_H (REG_DVI_EQ2_BASE + 0x21)
[all …]

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