Home
last modified time | relevance | path

Searched refs:REG_DVI_DTOP_DUAL_P3_63_L (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c1459 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1460 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2240 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2241 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c1489 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1490 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2270 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2271 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c1528 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1529 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2309 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2310 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c1489 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1490 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2270 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2271 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c1535 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1536 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2316 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2317 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c1528 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1529 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2309 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2310 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c1462 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1463 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2251 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2252 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c1462 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1463 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2251 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2252 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c1628 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1629 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2409 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2410 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c1462 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1463 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2251 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2252 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c1628 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1629 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2409 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2410 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h5369 #define REG_DVI_DTOP_DUAL_P3_63_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h5371 #define REG_DVI_DTOP_DUAL_P3_63_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h5363 #define REG_DVI_DTOP_DUAL_P3_63_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h5371 #define REG_DVI_DTOP_DUAL_P3_63_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h5363 #define REG_DVI_DTOP_DUAL_P3_63_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h5371 #define REG_DVI_DTOP_DUAL_P3_63_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h5371 #define REG_DVI_DTOP_DUAL_P3_63_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h5363 #define REG_DVI_DTOP_DUAL_P3_63_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h5364 #define REG_DVI_DTOP_DUAL_P3_63_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h5363 #define REG_DVI_DTOP_DUAL_P3_63_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h5369 #define REG_DVI_DTOP_DUAL_P3_63_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h5369 #define REG_DVI_DTOP_DUAL_P3_63_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h5369 #define REG_DVI_DTOP_DUAL_P3_63_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6) macro