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Searched refs:REG_DVI_DTOP_DUAL_P2_63_L (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c1445 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1446 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2235 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2236 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c1475 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1476 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2265 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2266 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c1513 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1514 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2304 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2305 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c1475 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1476 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2265 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2266 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c1520 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1521 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2311 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2312 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c1513 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1514 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2304 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2305 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c1448 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1449 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2246 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2247 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c1448 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1449 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2246 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2247 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c1613 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1614 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2404 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2405 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c1448 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1449 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2246 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2247 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c1613 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1614 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2404 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2405 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h4833 #define REG_DVI_DTOP_DUAL_P2_63_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h4835 #define REG_DVI_DTOP_DUAL_P2_63_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h4829 #define REG_DVI_DTOP_DUAL_P2_63_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h4835 #define REG_DVI_DTOP_DUAL_P2_63_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h4829 #define REG_DVI_DTOP_DUAL_P2_63_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h4835 #define REG_DVI_DTOP_DUAL_P2_63_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h4835 #define REG_DVI_DTOP_DUAL_P2_63_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h4829 #define REG_DVI_DTOP_DUAL_P2_63_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h4830 #define REG_DVI_DTOP_DUAL_P2_63_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h4829 #define REG_DVI_DTOP_DUAL_P2_63_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h4833 #define REG_DVI_DTOP_DUAL_P2_63_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h4833 #define REG_DVI_DTOP_DUAL_P2_63_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h4833 #define REG_DVI_DTOP_DUAL_P2_63_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6) macro