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Searched refs:REG_DVI_DTOP_DUAL_P1_63_L (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c1431 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1432 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2230 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2231 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c1461 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1462 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2260 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2261 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c1498 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1499 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2299 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2300 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c1461 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1462 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2260 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2261 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c1505 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1506 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2306 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2307 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c1498 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1499 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2299 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2300 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c1434 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1435 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2241 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2242 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c1434 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1435 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2241 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2242 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c1598 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1599 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2399 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2400 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c1434 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1435 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2241 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2242 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c1598 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_SetErrorCountStatus()
1599 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_SetErrorCountStatus()
2399 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, BIT(0), BIT(0)); in _Hal_tmds_ClearErrorCheck()
2400 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_63_L, 0, BIT(0)); in _Hal_tmds_ClearErrorCheck()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h4297 #define REG_DVI_DTOP_DUAL_P1_63_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h4299 #define REG_DVI_DTOP_DUAL_P1_63_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h4295 #define REG_DVI_DTOP_DUAL_P1_63_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h4299 #define REG_DVI_DTOP_DUAL_P1_63_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h4295 #define REG_DVI_DTOP_DUAL_P1_63_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h4299 #define REG_DVI_DTOP_DUAL_P1_63_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h4299 #define REG_DVI_DTOP_DUAL_P1_63_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h4295 #define REG_DVI_DTOP_DUAL_P1_63_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h4296 #define REG_DVI_DTOP_DUAL_P1_63_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h4295 #define REG_DVI_DTOP_DUAL_P1_63_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h4297 #define REG_DVI_DTOP_DUAL_P1_63_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h4297 #define REG_DVI_DTOP_DUAL_P1_63_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h4297 #define REG_DVI_DTOP_DUAL_P1_63_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6) macro