Home
last modified time | relevance | path

Searched refs:REG_DVI_DTOP_DUAL_P1_29_L (Results 1 – 22 of 22) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_mux.c229 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
248 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
275 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
298 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_mux.c229 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
248 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
275 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
298 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_mux.c229 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
248 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
275 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
298 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_mux.c229 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
248 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
275 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
298 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_mux.c229 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
248 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
275 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
298 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_mux.c229 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
248 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
275 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
298 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_mux.c229 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
248 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
275 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
298 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_mux.c229 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
248 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
275 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
298 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_mux.c229 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
248 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
275 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
298 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h4181 #define REG_DVI_DTOP_DUAL_P1_29_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h4183 #define REG_DVI_DTOP_DUAL_P1_29_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h4179 #define REG_DVI_DTOP_DUAL_P1_29_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h4183 #define REG_DVI_DTOP_DUAL_P1_29_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h4179 #define REG_DVI_DTOP_DUAL_P1_29_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h4183 #define REG_DVI_DTOP_DUAL_P1_29_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h4183 #define REG_DVI_DTOP_DUAL_P1_29_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h4179 #define REG_DVI_DTOP_DUAL_P1_29_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h4180 #define REG_DVI_DTOP_DUAL_P1_29_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h4179 #define REG_DVI_DTOP_DUAL_P1_29_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h4181 #define REG_DVI_DTOP_DUAL_P1_29_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h4181 #define REG_DVI_DTOP_DUAL_P1_29_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h4181 #define REG_DVI_DTOP_DUAL_P1_29_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x52) macro