| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 3330 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
3331 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
3354 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingReadDone()
3355 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingReadDone()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 3452 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
3453 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
3476 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingReadDone()
3477 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingReadDone()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 3367 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
3368 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
3395 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingReadDone()
3396 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingReadDone()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 3452 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
3453 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
3476 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingReadDone()
3477 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingReadDone()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 3347 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
3348 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
3371 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingReadDone()
3372 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingReadDone()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 3367 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
3368 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
3395 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingReadDone()
3396 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingReadDone()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 4000 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
4001 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
4024 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingReadDone()
4025 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingReadDone()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 4003 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
4004 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
4027 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingReadDone()
4028 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingReadDone()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 3536 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
3537 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
3560 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingReadDone()
3561 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingReadDone()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 4006 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
4007 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
4030 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingReadDone()
4031 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingReadDone()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 3536 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingWriteDone()
3537 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingWriteDone()
3560 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, BIT(14)); in Hal_HDCP22_PollingReadDone()
3561 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L + dwBKOffset, 0); in Hal_HDCP22_PollingReadDone()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 1413 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L, BIT(14)); in Hal_HDCP22_PollingWriteDone()
1414 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L, 0); in Hal_HDCP22_PollingWriteDone()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 2116 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L, BIT(14)); in Hal_HDCP22_PollingWriteDone()
2117 W2BYTE(REG_DVI_DTOP_DUAL_P0_3C_L, 0); in Hal_HDCP22_PollingWriteDone()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 3683 #define REG_DVI_DTOP_DUAL_P0_3C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x78) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 3685 #define REG_DVI_DTOP_DUAL_P0_3C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x78) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 3683 #define REG_DVI_DTOP_DUAL_P0_3C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x78) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 3685 #define REG_DVI_DTOP_DUAL_P0_3C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x78) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 3683 #define REG_DVI_DTOP_DUAL_P0_3C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x78) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 3685 #define REG_DVI_DTOP_DUAL_P0_3C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x78) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 3685 #define REG_DVI_DTOP_DUAL_P0_3C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x78) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 3683 #define REG_DVI_DTOP_DUAL_P0_3C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x78) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 3684 #define REG_DVI_DTOP_DUAL_P0_3C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x78) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 3683 #define REG_DVI_DTOP_DUAL_P0_3C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x78) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 3683 #define REG_DVI_DTOP_DUAL_P0_3C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x78) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 3683 #define REG_DVI_DTOP_DUAL_P0_3C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x78) macro
|