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Searched refs:REG_DVI_DTOP_DUAL_P0_29_L (Results 1 – 25 of 35) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_mux.c226 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
252 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
277 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
302 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c3148 W2BYTEMSK( REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_mux.c226 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
252 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
277 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
302 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c5534 W2BYTEMSK( REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated (b-ch) in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_mux.c226 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
252 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
277 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
302 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c3885 W2BYTEMSK( REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_mux.c226 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
252 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
277 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
302 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c6243 W2BYTEMSK( REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated (b-ch) in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_mux.c226 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
252 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
277 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
302 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c6240 W2BYTEMSK( REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated (b-ch) in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_mux.c226 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
252 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
277 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
302 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c5955 W2BYTEMSK( REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated (b-ch) in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_mux.c226 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
252 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
277 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
302 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c5955 W2BYTEMSK( REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated (b-ch) in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_mux.c226 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
252 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
277 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
302 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c6237 W2BYTEMSK( REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated (b-ch) in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_mux.c226 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
252 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
277 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
302 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c5649 W2BYTEMSK( REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated (b-ch) in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c5609 W2BYTEMSK( REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated (b-ch) in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c5688 W2BYTEMSK( REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated (b-ch) in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c5609 W2BYTEMSK( REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated (b-ch) in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c5688 W2BYTEMSK( REG_DVI_DTOP_DUAL_P0_29_L, 0, BIT(15)); // [15]: turn off slowly updated (b-ch) in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h3645 #define REG_DVI_DTOP_DUAL_P0_29_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h3647 #define REG_DVI_DTOP_DUAL_P0_29_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h3645 #define REG_DVI_DTOP_DUAL_P0_29_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x52) macro

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