| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 2014 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_21_L, 0, BIT(1)); // [1]: enable of clk stable gate in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 2750 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_21_L, 0, BIT(1)); // [1]: enable of clk stable gate in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 4220 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_21_L + u16bank_offset, 0, BIT(1)); // [1]: enable of clk stable gate in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 4329 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_21_L + u16bank_offset, 0, BIT(1)); // [1]: enable of clk stable gate in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 4327 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_21_L + u16bank_offset, 0, BIT(1)); // [1]: enable of clk stable gate in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 4329 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_21_L + u16bank_offset, 0, BIT(1)); // [1]: enable of clk stable gate in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 4271 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_21_L + u16bank_offset, 0, BIT(1)); // [1]: enable of clk stable gate in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 4327 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_21_L + u16bank_offset, 0, BIT(1)); // [1]: enable of clk stable gate in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 4900 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_21_L + u16bank_offset, 0, BIT(1)); // [1]: enable of clk stable gate in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 4903 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_21_L + u16bank_offset, 0, BIT(1)); // [1]: enable of clk stable gate in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 4455 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_21_L + u16bank_offset, 0, BIT(1)); // [1]: enable of clk stable gate in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 4906 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_21_L + u16bank_offset, 0, BIT(1)); // [1]: enable of clk stable gate in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 4455 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_21_L + u16bank_offset, 0, BIT(1)); // [1]: enable of clk stable gate in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 3629 #define REG_DVI_DTOP_DUAL_P0_21_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x42) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 3631 #define REG_DVI_DTOP_DUAL_P0_21_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x42) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 3629 #define REG_DVI_DTOP_DUAL_P0_21_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x42) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 3631 #define REG_DVI_DTOP_DUAL_P0_21_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x42) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 3629 #define REG_DVI_DTOP_DUAL_P0_21_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x42) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 3631 #define REG_DVI_DTOP_DUAL_P0_21_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x42) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 3631 #define REG_DVI_DTOP_DUAL_P0_21_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x42) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 3629 #define REG_DVI_DTOP_DUAL_P0_21_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x42) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 3630 #define REG_DVI_DTOP_DUAL_P0_21_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x42) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 3629 #define REG_DVI_DTOP_DUAL_P0_21_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x42) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 3629 #define REG_DVI_DTOP_DUAL_P0_21_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x42) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 3629 #define REG_DVI_DTOP_DUAL_P0_21_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x42) macro
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