| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 602 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, BIT(3), BIT(3)); in _Hal_tmds_SetErrorCountStatus()
603 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, 0, BIT(3)); in _Hal_tmds_SetErrorCountStatus()
1899 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, BIT(1), BMASK(1:0)); // [1:0]: DVI select channel2(R) as smal… in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 769 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, BIT(3), BIT(3)); in _Hal_tmds_SetErrorCountStatus()
770 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, 0, BIT(3)); in _Hal_tmds_SetErrorCountStatus()
2634 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, BIT(1), BMASK(1:0)); // [1:0]: DVI select channel2(R) as smal… in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 1410 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, BIT(3), BIT(3)); in _Hal_tmds_SetErrorCountStatus()
1411 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, 0, BIT(3)); in _Hal_tmds_SetErrorCountStatus()
4046 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L + u16bank_offset, BIT(1), BMASK(1:0)); // [1:0]: DVI select ch… in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 1440 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, BIT(3), BIT(3)); in _Hal_tmds_SetErrorCountStatus()
1441 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, 0, BIT(3)); in _Hal_tmds_SetErrorCountStatus()
4151 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L + u16bank_offset, BIT(1), BMASK(1:0)); // [1:0]: DVI select ch… in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 1476 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, BIT(3), BIT(3)); in _Hal_tmds_SetErrorCountStatus()
1477 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, 0, BIT(3)); in _Hal_tmds_SetErrorCountStatus()
4160 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L + u16bank_offset, BIT(1), BMASK(1:0)); // [1:0]: DVI select ch… in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 1440 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, BIT(3), BIT(3)); in _Hal_tmds_SetErrorCountStatus()
1441 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, 0, BIT(3)); in _Hal_tmds_SetErrorCountStatus()
4151 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L + u16bank_offset, BIT(1), BMASK(1:0)); // [1:0]: DVI select ch… in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 1483 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, BIT(3), BIT(3)); in _Hal_tmds_SetErrorCountStatus()
1484 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, 0, BIT(3)); in _Hal_tmds_SetErrorCountStatus()
4091 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L + u16bank_offset, BIT(1), BMASK(1:0)); // [1:0]: DVI select ch… in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 1476 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, BIT(3), BIT(3)); in _Hal_tmds_SetErrorCountStatus()
1477 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, 0, BIT(3)); in _Hal_tmds_SetErrorCountStatus()
4160 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L + u16bank_offset, BIT(1), BMASK(1:0)); // [1:0]: DVI select ch… in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 1413 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, BIT(3), BIT(3)); in _Hal_tmds_SetErrorCountStatus()
1414 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, 0, BIT(3)); in _Hal_tmds_SetErrorCountStatus()
4722 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L + u16bank_offset, BIT(1), BMASK(1:0)); // [1:0]: DVI select ch… in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 1413 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, BIT(3), BIT(3)); in _Hal_tmds_SetErrorCountStatus()
1414 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, 0, BIT(3)); in _Hal_tmds_SetErrorCountStatus()
4725 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L + u16bank_offset, BIT(1), BMASK(1:0)); // [1:0]: DVI select ch… in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 1576 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, BIT(3), BIT(3)); in _Hal_tmds_SetErrorCountStatus()
1577 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, 0, BIT(3)); in _Hal_tmds_SetErrorCountStatus()
4282 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L + u16bank_offset, BIT(1), BMASK(1:0)); // [1:0]: DVI select ch… in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 1413 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, BIT(3), BIT(3)); in _Hal_tmds_SetErrorCountStatus()
1414 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, 0, BIT(3)); in _Hal_tmds_SetErrorCountStatus()
4728 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L + u16bank_offset, BIT(1), BMASK(1:0)); // [1:0]: DVI select ch… in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 1576 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, BIT(3), BIT(3)); in _Hal_tmds_SetErrorCountStatus()
1577 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L, 0, BIT(3)); in _Hal_tmds_SetErrorCountStatus()
4282 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_0B_L + u16bank_offset, BIT(1), BMASK(1:0)); // [1:0]: DVI select ch… in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 3585 #define REG_DVI_DTOP_DUAL_P0_0B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x16) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 3587 #define REG_DVI_DTOP_DUAL_P0_0B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x16) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 3585 #define REG_DVI_DTOP_DUAL_P0_0B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x16) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 3587 #define REG_DVI_DTOP_DUAL_P0_0B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x16) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 3585 #define REG_DVI_DTOP_DUAL_P0_0B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x16) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 3587 #define REG_DVI_DTOP_DUAL_P0_0B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x16) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 3587 #define REG_DVI_DTOP_DUAL_P0_0B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x16) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 3585 #define REG_DVI_DTOP_DUAL_P0_0B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x16) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 3586 #define REG_DVI_DTOP_DUAL_P0_0B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x16) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 3585 #define REG_DVI_DTOP_DUAL_P0_0B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x16) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 3585 #define REG_DVI_DTOP_DUAL_P0_0B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x16) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 3585 #define REG_DVI_DTOP_DUAL_P0_0B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x16) macro
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