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Searched refs:REG_DVI_DTOP_2A_L (Results 1 – 25 of 29) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_mux.c230 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0xE3E3, HBMASK|LBMASK); // [15:8]: update Rch slowly, [7:0]:update G… in Hal_SC_mux_set_dvi_mux()
234 W2BYTE( REG_DVI_DTOP_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
273 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0, BIT(15)|BIT(7)); // [15]: turn off slowly updated, [7]: turn off … in Hal_SC_mux_set_dvi_mux()
311 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0, BIT(15)|BIT(7)); // [15]: turn off slowly updated, [7]: turn off … in Hal_SC_mux_set_dvi_mux()
348 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0, BIT(15)|BIT(7)); // [15]: turn off slowly updated, [7]: turn off … in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c1131 W2BYTE( REG_DVI_DTOP_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_HDMI_init()
1155 W2BYTE( REG_DVI_DTOP_2A_L, 0xE3E3); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_HDMI_init()
2697 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0, BIT(15)|BIT(7)); // [15]: turn off slowly updated, [7]: turn off … in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_mux.c230 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0xE3E3, HBMASK|LBMASK); // [15:8]: update Rch slowly, [7:0]:update G… in Hal_SC_mux_set_dvi_mux()
234 W2BYTE( REG_DVI_DTOP_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_SC_mux_set_dvi_mux()
273 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0, BIT(15)|BIT(7)); // [15]: turn off slowly updated, [7]: turn off … in Hal_SC_mux_set_dvi_mux()
311 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0, BIT(15)|BIT(7)); // [15]: turn off slowly updated, [7]: turn off … in Hal_SC_mux_set_dvi_mux()
348 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0, BIT(15)|BIT(7)); // [15]: turn off slowly updated, [7]: turn off … in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c1131 W2BYTE( REG_DVI_DTOP_2A_L, 0); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_HDMI_init()
1155 W2BYTE( REG_DVI_DTOP_2A_L, 0xE3E3); // [15:8]: update Rch slowly, [7:0]:update Gch slowly in Hal_HDMI_init()
2697 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0, BIT(15)|BIT(7)); // [15]: turn off slowly updated, [7]: turn off … in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_hdmi.c3264 W2BYTE(REG_DVI_DTOP_2A_L, 0x0000); in MDrv_HDMI_SetUpdatePhaseLineCount_U2()
3271 W2BYTE(REG_DVI_DTOP_2A_L, 0); in MDrv_HDMI_SetUpdatePhaseLineCount_U2()
3282 W2BYTE(REG_DVI_DTOP_2A_L, 0x0000); in MDrv_HDMI_SetUpdatePhaseLineCount_U2()
3288 W2BYTE(REG_DVI_DTOP_2A_L, 0); in MDrv_HDMI_SetUpdatePhaseLineCount_U2()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_mux.c223 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0xE3E3, HBMASK|LBMASK); // [15:8]: update Rch slowly, [7:0]:update G… in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_mux.c223 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0xE3E3, HBMASK|LBMASK); // [15:8]: update Rch slowly, [7:0]:update G… in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_mux.c223 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0xE3E3, HBMASK|LBMASK); // [15:8]: update Rch slowly, [7:0]:update G… in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_mux.c223 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0xE3E3, HBMASK|LBMASK); // [15:8]: update Rch slowly, [7:0]:update G… in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_mux.c223 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0xE3E3, HBMASK|LBMASK); // [15:8]: update Rch slowly, [7:0]:update G… in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_mux.c223 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0xE3E3, HBMASK|LBMASK); // [15:8]: update Rch slowly, [7:0]:update G… in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_mux.c223 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0xE3E3, HBMASK|LBMASK); // [15:8]: update Rch slowly, [7:0]:update G… in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_mux.c223 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0xE3E3, HBMASK|LBMASK); // [15:8]: update Rch slowly, [7:0]:update G… in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_mux.c223 …W2BYTEMSK( REG_DVI_DTOP_2A_L, 0xE3E3, HBMASK|LBMASK); // [15:8]: update Rch slowly, [7:0]:update G… in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h186 #define REG_DVI_DTOP_2A_L (REG_DVI_DTOP_BASE + 0x54) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h186 #define REG_DVI_DTOP_2A_L (REG_DVI_DTOP_BASE + 0x54) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h186 #define REG_DVI_DTOP_2A_L (REG_DVI_DTOP_BASE + 0x54) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h186 #define REG_DVI_DTOP_2A_L (REG_DVI_DTOP_BASE + 0x54) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h186 #define REG_DVI_DTOP_2A_L (REG_DVI_DTOP_BASE + 0x54) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h186 #define REG_DVI_DTOP_2A_L (REG_DVI_DTOP_BASE + 0x54) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h186 #define REG_DVI_DTOP_2A_L (REG_DVI_DTOP_BASE + 0x54) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h186 #define REG_DVI_DTOP_2A_L (REG_DVI_DTOP_BASE + 0x54) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h186 #define REG_DVI_DTOP_2A_L (REG_DVI_DTOP_BASE + 0x54) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h186 #define REG_DVI_DTOP_2A_L (REG_DVI_DTOP_BASE + 0x54) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h186 #define REG_DVI_DTOP_2A_L (REG_DVI_DTOP_BASE + 0x54) macro

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