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Searched refs:REG_DVI_DTOP3_25_L (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c2769 W2BYTEMSK(REG_DVI_DTOP3_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
2774 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
2780 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c3506 W2BYTEMSK(REG_DVI_DTOP3_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
3511 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
3517 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_hdmi.c3628 W2BYTEMSK(REG_DVI_DTOP3_25_L, BIT(6), BIT(6)); in Hal_HDMI_StablePolling()
3630 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(6)); in Hal_HDMI_StablePolling()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_hdmi.c3628 W2BYTEMSK(REG_DVI_DTOP3_25_L, BIT(6), BIT(6)); in Hal_HDMI_StablePolling()
3630 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(6)); in Hal_HDMI_StablePolling()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c5128 W2BYTEMSK(REG_DVI_DTOP3_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5133 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5139 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c5228 W2BYTEMSK(REG_DVI_DTOP3_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5233 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5239 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c5266 W2BYTEMSK(REG_DVI_DTOP3_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5271 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5277 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c5228 W2BYTEMSK(REG_DVI_DTOP3_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5233 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5239 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c5239 W2BYTEMSK(REG_DVI_DTOP3_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5244 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5250 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c5266 W2BYTEMSK(REG_DVI_DTOP3_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5271 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5277 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c5831 W2BYTEMSK(REG_DVI_DTOP3_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5836 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5842 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c5834 W2BYTEMSK(REG_DVI_DTOP3_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5839 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5845 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c5537 W2BYTEMSK(REG_DVI_DTOP3_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5542 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5548 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c5837 W2BYTEMSK(REG_DVI_DTOP3_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5842 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5848 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c5537 W2BYTEMSK(REG_DVI_DTOP3_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5542 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5548 W2BYTEMSK(REG_DVI_DTOP3_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h380 #define REG_DVI_DTOP3_25_L (REG_DVI_DTOP3_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h380 #define REG_DVI_DTOP3_25_L (REG_DVI_DTOP3_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h374 #define REG_DVI_DTOP3_25_L (REG_DVI_DTOP3_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h374 #define REG_DVI_DTOP3_25_L (REG_DVI_DTOP3_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h374 #define REG_DVI_DTOP3_25_L (REG_DVI_DTOP3_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h374 #define REG_DVI_DTOP3_25_L (REG_DVI_DTOP3_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h374 #define REG_DVI_DTOP3_25_L (REG_DVI_DTOP3_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h374 #define REG_DVI_DTOP3_25_L (REG_DVI_DTOP3_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h374 #define REG_DVI_DTOP3_25_L (REG_DVI_DTOP3_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h374 #define REG_DVI_DTOP3_25_L (REG_DVI_DTOP3_BASE + 0x4A) macro

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