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Searched refs:REG_DVI_DTOP2_25_L (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c2810 W2BYTEMSK(REG_DVI_DTOP2_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
2815 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
2821 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c3547 W2BYTEMSK(REG_DVI_DTOP2_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
3552 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
3558 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_hdmi.c3686 W2BYTEMSK(REG_DVI_DTOP2_25_L, BIT(6), BIT(6)); in Hal_HDMI_StablePolling()
3688 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(6)); in Hal_HDMI_StablePolling()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_hdmi.c3686 W2BYTEMSK(REG_DVI_DTOP2_25_L, BIT(6), BIT(6)); in Hal_HDMI_StablePolling()
3688 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(6)); in Hal_HDMI_StablePolling()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c5169 W2BYTEMSK(REG_DVI_DTOP2_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5174 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5180 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c5269 W2BYTEMSK(REG_DVI_DTOP2_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5274 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5280 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c5307 W2BYTEMSK(REG_DVI_DTOP2_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5312 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5318 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c5269 W2BYTEMSK(REG_DVI_DTOP2_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5274 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5280 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c5280 W2BYTEMSK(REG_DVI_DTOP2_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5285 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5291 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c5307 W2BYTEMSK(REG_DVI_DTOP2_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5312 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5318 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c5872 W2BYTEMSK(REG_DVI_DTOP2_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5877 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5883 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c5875 W2BYTEMSK(REG_DVI_DTOP2_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5880 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5886 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c5578 W2BYTEMSK(REG_DVI_DTOP2_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5583 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5589 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c5878 W2BYTEMSK(REG_DVI_DTOP2_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5883 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5889 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c5578 W2BYTEMSK(REG_DVI_DTOP2_25_L, BIT(5), BIT(5)); in Hal_DVI_HF_adjust()
5583 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
5589 W2BYTEMSK(REG_DVI_DTOP2_25_L, 0, BIT(5)); in Hal_DVI_HF_adjust()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h312 #define REG_DVI_DTOP2_25_L (REG_DVI_DTOP2_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h312 #define REG_DVI_DTOP2_25_L (REG_DVI_DTOP2_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h306 #define REG_DVI_DTOP2_25_L (REG_DVI_DTOP2_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h306 #define REG_DVI_DTOP2_25_L (REG_DVI_DTOP2_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h306 #define REG_DVI_DTOP2_25_L (REG_DVI_DTOP2_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h306 #define REG_DVI_DTOP2_25_L (REG_DVI_DTOP2_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h306 #define REG_DVI_DTOP2_25_L (REG_DVI_DTOP2_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h306 #define REG_DVI_DTOP2_25_L (REG_DVI_DTOP2_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h306 #define REG_DVI_DTOP2_25_L (REG_DVI_DTOP2_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h306 #define REG_DVI_DTOP2_25_L (REG_DVI_DTOP2_BASE + 0x4A) macro

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